s71ws256jc0 Meet Spansion Inc., s71ws256jc0 Datasheet - Page 175

• Manufacturer Part Number: s71ws256jc0
• Description: Stacked Multi-chip Product Mcp 128/64 Megabit 8m/4m X 16-bit Cmos 1.8 Volt-only, Simultaneous Read/write, Burst Mode Flash Memory With Cellularram
• Manufacturer: Meet Spansion Inc.

38 Low-Power Operation
38.1
38.2 Temperature Compensated Refresh
38.3 Partial Array Refresh
174
Standby Mode Operation
During standby, the device current consumption is reduced to the level necessary to perform the
DRAM refresh operation on the full array. Standby operation occurs when CE# and ZZ# are HIGH.
The device enters a reduced power state during READ and WRITE operations where the address
and control inputs remain static for an extended period of time. This mode continues until a
change occurs to the address or control inputs.
Temperature-Compensated Refresh (TCR) allows for adequate refresh at different temperatures.
This CellularRAM device includes an on-chip temperature sensor. When the sensor is enabled, it
continually adjusts the refresh rate according to the operating temperature. The on-chip sensor
is enabled by default.
Three fixed refresh rates are also available, corresponding to temperature thresholds of +15° C,
+45° C, and +85° C. The setting selected must be for a temperature higher than the case tem-
perature of the CellularRAM device. If the case temperature is +35° C, the system can minimize
self-refresh current consumption by selecting the +45° C setting. The +15° C setting may result
in inadequate refreshing and cause data corruption.
Partial Array Refresh (PAR) restricts refresh operation to a portion of the total memory array. This
feature enables the system to reduce refresh current by only refreshing that part of the memory
array that is absolutely necessary. The refresh options are full array, one-half array, one-quarter
array, one-eighth array, or none of the array. Data stored in addresses not receiving refresh be-
come corrupted. The mapping of these partitions can start at either the beginning or the end of
the address map
nored during PAR operation.
The device only enters PAR mode if the SLEEP bit in the CR has been set HIGH (CR[4] = 1). PAR
can be initiated by bring the ZZ# ball to the LOW state for longer than 10 µs. Returning ZZ# to
HIGH causes an exit from PAR and the entire array is immediately available for READ and WRITE
operations.
Alternatively, PAR can be initiated using the CR software access sequence (see
to the Configuration Register
“1” using this method. However, using software access to write to the CR alters the function of
ZZ# so that ZZ# LOW no longer initiates PAR, although ZZ# continues to enable WRITEs to the
CR. This functional change persists until the next time the device is powered up (see
(Table 39.1
Aysnc/Page CellularRAM Type 2
A d v a n c e
and
on
page
Table 39.2 on page
176). PAR is enabled immediately upon setting CR[4] to
I n f o r m a t i o n
179). READ and WRITE operations are ig-
CellRAM_05_A0 August 25, 2005
Software Access
Figure
38.1).