s71ws256jc0 Meet Spansion Inc., s71ws256jc0 Datasheet - Page 126

• Manufacturer Part Number: s71ws256jc0
• Description: Stacked Multi-chip Product Mcp 128/64 Megabit 8m/4m X 16-bit Cmos 1.8 Volt-only, Simultaneous Read/write, Burst Mode Flash Memory With Cellularram
• Manufacturer: Meet Spansion Inc.

27.6 LB#/UB# Operation
Note: Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay.
March 9, 2005 CellRam_03_A0
LB#/UB#
DQ[15:0]
A[22:0]
ADV#
WAIT
WE#
CE#
OE#
CLK
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V OH
V OL
V OH
V OL
Once a Read or Write operation has been initiated, Wait goes active to indicate that the Cellular-
RAM device requires additional time before data can be transferred. For Read operations, Wait will
remain active until valid data is output from the device. For Write operations, Wait will indicate to
the memory controller when data will be accepted into the CellularRAM device. When Wait tran-
sitions to an inactive state, the data burst will progress on successive clock edges.
CE# must remain asserted during Wait cycles (Wait asserted and Wait configuration BCR[8] = 1).
Bringing CE# High during Wait cycles may cause data corruption. (Note that for BCR[8] = 0, the
actual Wait cycles end one cycle after Wait de-asserts, and for row boundary crossings, start one
cycle after the Wait signal asserts.)
The WAIT output also performs an arbitration role when a Read or Write operation is launched
while an on-chip refresh is in progress. If a collision occurs, the Wait pin is asserted for additional
clock cycles until the refresh has completed
eration has completed, the Read or Write operation will continue normally.
Wait is also asserted when a continuous Read or Write burst crosses the boundary between 128-
word rows. The Wait assertion allows time for the new row to be accessed, and permits any pend-
ing refresh operations to be performed.
The LB# enable and UB# enable signals support byte-wide data transfers. During Read opera-
tions, the enabled byte(s) are driven onto the DQs. The DQs associated with a disabled byte are
put into a High-Z state during a Read operation. During Write operations, any disabled bytes will
not be transferred to the RAM array and the internal value will remain unchanged. During an asyn-
chronous Write cycle, the data to be written is latched on the rising edge of CE#, WE#, LB#, or
UB#, whichever occurs first.
When both the LB# and UB# are disabled (High) during an operation, the device will disable the
data bus from receiving or transmitting data. Although the device will seem to be deselected, it
remains in an active mode as long as CE# remains Low.
High-Z
Additional WAIT states inserted to allow refresh completion.
Address
A d v a n c e
Valid
Figure 27.7 Refresh Collision During Read Operation
I n f o r m a t i o n
CellularRAM Type 2
(Figure 27.7
D[0]
Legend:
and
D[1]
Figure
Don't care
27.8). When the refresh op-
D[2]
D[3]
Undefined
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