s71ws256jc0 Meet Spansion Inc., s71ws256jc0 Datasheet - Page 150

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s71ws256jc0

Manufacturer Part Number
s71ws256jc0
Description
Stacked Multi-chip Product Mcp 128/64 Megabit 8m/4m X 16-bit Cmos 1.8 Volt-only, Simultaneous Read/write, Burst Mode Flash Memory With Cellularram
Manufacturer
Meet Spansion Inc.
Datasheet
Note: Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay. Clock
rates below 50MHz (t
March 9, 2005 CellRam_03_A0
DQ[15:0]
LB#/UB#
A[22:0]
WAIT
ADV#
WE#
OE#
CE#
CLK
V OH
V OL
V OH
V OL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
CLK
Figure 33.5 Single-Access Burst Read Operation—Variable Latency
> 20ns) are allowed as long as t
READ Burst Identified
VALID ADDRESS
High-Z
A d v a n c e
t SP
t CSP
(WE# = HIGH)
t SP
t SP
t SP
t CEW
t KHKL
t HD
t HD
t HD
t HD
High-Z
t CLK
I n f o r m a t i o n
CellularRAM Type 2
t ABA
t KP
CSP
specifications are met.
t OLZ
t BOE
t ACLK
t KHTL
Legend:
VALID OUTPUT
t HD
t KP
Don't Care
t KOH
t OHZ
t HZ
High-Z
Undefined
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