s71ws256jc0 Meet Spansion Inc., s71ws256jc0 Datasheet - Page 65

• Manufacturer Part Number: s71ws256jc0
• Description: Stacked Multi-chip Product Mcp 128/64 Megabit 8m/4m X 16-bit Cmos 1.8 Volt-only, Simultaneous Read/write, Burst Mode Flash Memory With Cellularram
• Manufacturer: Meet Spansion Inc.

14 Command Definitions
14.1
14.2
June 24, 2005 S29WS-J_M0_A4
Reading Array Data
Set Configuration Register Command Sequence
Writing specific address and data commands or sequences into the command register initiates
device operations.
mand sequences. Writing incorrect address and data values or writing them in the improper
sequence may place the device in an unknown state. The system must write the reset command
to return the device to reading array data. Refer to the AC Characteristics section for timing
diagrams.
The device is automatically set to reading array data after device power-up. No commands are
required to retrieve data in asynchronous mode. Each bank is ready to read array data after com-
pleting an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the corresponding bank enters the erase-
suspend-read mode, after which the system can read data from any non-erase-suspended sector
within the same bank. After completing a programming operation in the Erase Suspend mode,
the system may once again read array data from any non-erase-suspended sector within the
same bank. See the “Erase Suspend/Erase Resume Commands” section on page 72 for more
information.
The system must issue the reset command to return a bank to the read (or erase-suspend-read)
mode if DQ5 goes high during an active program or erase operation, or if the bank is in the au-
toselect mode. See the “Reset Command” section on page 67 for more information.
See also “Requirements for Asynchronous ReadOperation (Non-Burst)” section on page 28 and
“Requirements for Synchronous (Burst) Read Operation” section on page 29 for more informa-
tion. The Asynchronous Read and Synchronous/Burst Read tables provide the read parameters,
and
Figure 22.5, “Synchronous Burst Mode Read,” on page
Read with Latched Addresses,” on page 96
The device uses a configuration register to set the various burst parameters: number of wait
states, burst read mode, active clock edge, RDY configuration, and synchronous mode active. The
configuration register must be set before the device will enter burst mode.
The configuration register is loaded with a three-cycle command sequence. The first two cycles
are standard unlock sequences. On the third cycle, the data should be C0h, address bits A11–A0
should be 555h, and address bits A19–A12 set the code to be latched. The device will power up
or after a hardware reset with the default setting, which is in asynchronous mode. The register
must be set before the device can enter synchronous mode. The configuration register can not
be changed during device operations (program, erase, or sector lock).
Figure 22.3, “CLK Synchronous Burst Mode Read (rising active CLK),” on page
Table 14.5, “Command Definitions,” on page 77
D a t a
S h e e t
S29WS128J/064J
show the timings.
94, and
Figure 22.8, “Asynchronous Mode
defines the valid register com-
93,
63