s71ws256jc0 Meet Spansion Inc., s71ws256jc0 Datasheet - Page 174

• Manufacturer Part Number: s71ws256jc0
• Description: Stacked Multi-chip Product Mcp 128/64 Megabit 8m/4m X 16-bit Cmos 1.8 Volt-only, Simultaneous Read/write, Burst Mode Flash Memory With Cellularram
• Manufacturer: Meet Spansion Inc.

37.2 Page Mode Read Operation
37.3 LB#/UB# Operation
August 25, 2005 CellRAM_05_A0
Page mode is a performance-enhancing extension to the legacy asynchronous READ operation.
In page-mode-capable products, an initial asynchronous read access is performed, then adjacent
addresses can be quickly read by simply changing the low-order address. Addresses A[3:0] are
used to determine the members of the 16-address CellularRAM page. Any change in addresses
A[4] or higher initiates a new t
access. Page mode takes advantage of the fact that adjacent addresses can be read in a shorter
period of time than random addresses. WRITE operations do not include comparable page mode
functionality. The CE# LOW time is limited by refresh considerations. CE# must not stay LOW
longer than t
The Lower Byte (LB#) enable and Upper Byte (UB#) enable signals allow for byte-wide data
transfers. During READ operations, enabled bytes are driven onto the DQs. The DQs associated
with a disabled byte are put into a High-Z state during a READ operation. During WRITE opera-
tions, any disabled bytes are not transferred to the memory array; the internal value remains
unchanged. During a WRITE cycle, the data to be written is latched on the rising edge of CE#,
WE#, LB#, or UB#, whichever occurs first. When both the LB# and UB# are disabled (HIGH) dur-
ing an operation, the device disables the data bus from receiving or transmitting data. Although
the device seems to be deselected, the device remains in an active mode as long as CE# remains
LOW.
A d v a n c e
CEM
.
A DDRESS
LB#/UB#
DATA
WE#
Aysnc/Page CellularRAM Type 2
OE#
CE#
Figure 37.3 Page Mode READ Operation
I n f o r m a t i o n
AA
access.
ADDRESS[0]
Figure 37.3
t AA
D[0]
ADDRESS
t APA
[1]
< t CEM
D[1]
shows the timing diagram for a page mode
ADDRESS
t APA
[2]
D[2]
ADDRESS
t APA
[3]
D[3]
DON’T CARE
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