s71ws256jc0 Meet Spansion Inc., s71ws256jc0 Datasheet - Page 76

• Manufacturer Part Number: s71ws256jc0
• Description: Stacked Multi-chip Product Mcp 128/64 Megabit 8m/4m X 16-bit Cmos 1.8 Volt-only, Simultaneous Read/write, Burst Mode Flash Memory With Cellularram
• Manufacturer: Meet Spansion Inc.

14.12 Password Verify Command
14.13 Password Protection Mode Locking Bit Program Command
14.14 Persistent Sector Protection Mode Locking Bit Program
14.15 Secured Silicon Sector Protection Bit Program Command
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Command
The Password Verify Command is used to verify the Password. The Password is verifiable only
when the Password Mode Locking Bit is not programmed. If the Password Mode Locking Bit is pro-
grammed and the user attempts to verify the Password, the device will always drive all F’s onto
the DQ data bus.
Also, the device will not operate in Simultaneous Operation when the Password Verify command
is executed. Only the password is returned regardless of the bank address. The lower two address
bits (A1–A0) are valid during the Password Verify. Writing the Secured Silicon Exit command re-
turns the device back to normal operation.
The Password Protection Mode Locking Bit Program Command programs the Password Protection
Mode Locking Bit, which prevents further verifies or updates to the password. Once programmed,
the Password Protection Mode Locking Bit cannot be erased and the Persistent Protection Mode
Locking Bit program circuitry is disabled, thereby forcing the device to remain in the Password
Protection Mode. After issuing “PL/68h” at the fourth bus cycle, the device requires a time out
period of approximately 150 µs for programming the Password Protection Mode Locking Bit. Then
by writing “PL/48h” at the fifth bus cycle, the device outputs verify data at DQ0. If DQ0 = 1, then
the Password Protection Mode Locking Bit is programmed. If not, the system must repeat this
program sequence from the fourth cycle of “PL/68h”. Exiting the Password Protection Mode Lock-
ing Bit Program command is accomplished by writing the Secured Silicon Sector Exit command
or Read/Reset command.
The Persistent Sector Protection Mode Locking Bit Program Command programs the Persistent
Sector Protection Mode Locking Bit, which prevents the Password Mode Locking Bit from ever
being programmed. By disabling the program circuitry of the Password Mode Locking Bit, the de-
vice is forced to remain in the Persistent Sector Protection mode of operation, once this bit is set.
After issuing “SL/68h” at the fourth bus cycle, the device requires a time out period of approxi-
mately 150 µs for programming the Persistent Protect ion Mode Locking Bit. Then by writ ing
“SMPL/48h” at the fifth bus cycle, the device outputs verify data at DQ0. If DQ0 = 1, then the
Persistent Protection Mode Locking Bit is programmed. If not, the system must repeat this pro-
gram sequence from the fourth cycle of “PL/68h”. Exiting the Persistent Protection Mode Locking
Bit Program command is accomplished by writing the Secured Silicon Sector Exit command or
Read/Reset command.
To protect the Secured Silicon Sector, write the Secured Silicon Sector Protect command sequence
while in the Secured Silicon Sector mode. After issuing “OW/48h” at the fourth bus cycle, the de-
vice requires a time out period of approximately 150 µs to protect the Secured Silicon Sector.
Then, by writing “OPBP/48” at the fifth bus cycle, the device outputs verify data at DQ0. If DQ0
= 1, then the Secured Silicon Sector is protected. If not, then the system must repeat this pro-
gram sequence from the fourth cycle of “OPBP/48h”. Exiting the Secured Silicon Sector Protection
Mode Locking Bit Program command is accomplished by writing the Secured Silicon Sector Exit
command or Read/Reset command.
S29WS128J/064J
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S29WS-J_M0_A4 June 24, 2005