s71ws256jc0 Meet Spansion Inc., s71ws256jc0 Datasheet - Page 137

• Manufacturer Part Number: s71ws256jc0
• Description: Stacked Multi-chip Product Mcp 128/64 Megabit 8m/4m X 16-bit Cmos 1.8 Volt-only, Simultaneous Read/write, Burst Mode Flash Memory With Cellularram
• Manufacturer: Meet Spansion Inc.

136
RCR[2]
29.4.2
29.4.3
29.4.4
1
1
1
1
RCR[1]
Deep Power-Down (RCR[4]): Default = DPD Disabled
The deep power-down bit enables and disables all refresh-related activity. This mode is used if
the system does not require the storage provided by the CellularRAM device. Any stored data will
become corrupted when DPD is enabled. When refresh activity has been re-enabled, the Cellular-
RAM device will require 150µs to perform an initialization procedure before normal operations can
resume.
Deep power-down is enabled when RCR[4] = 0, and remains enabled until RCR[4] is set to 1.
Temperature Compensated Refresh (RCR[6:5]): Default = +85ºC
Operation
The TCR bits allow for adequate refresh at four different temperature thresholds (+15ºC, +45ºC,
+70ºC, and +85ºC). The setting selected must be for a temperature higher than the case tem-
perature of the CellurlarRAM device. If the case temperature is +50ºC, the system can minimize
self refresh current consumption by selecting the +70ºC setting. The +15ºC and +45ºC settings
would result in inadequate refreshing and cause data corruption.
Page Mode Operation (RCR[7]): Default = Disabled
The page mode operation bit determines whether page mode is enabled for asynchronous Read
operations. In the power-up default state, page mode is disabled.
0
0
1
1
Table 29.5 64Mb Address Patterns for PAR (RCR[4] = 1) (Continued)
RCR[0]
0
1
0
1
One-quarter of die
One-eighth of die
One-half of die
Active Section
None of die
A d v a n c e
CellularRAM Type 2
I n f o r m a t i o n
100000h–3FFFFFh
200000h–3FFFFFh
300000h–3FFFFFh
Address Space
0
0 Meg x 16
2 Meg x 16
1 Meg x 16
512 K x 16
Size
CellRam_03_A0 March 9, 2005
Density
32Mb
16Mb
0Mb
8Mb