am42bds6408h Meet Spansion Inc., am42bds6408h Datasheet
am42bds6408h
Related parts for am42bds6408h
am42bds6408h Summary of contents
Page 1
... Am42BDS6408H Data Sheet July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to customers of both AMD and Fujitsu ...
Page 2
THIS PAGE LEFT INTENTIONALLY BLANK. ...
Page 3
... ADVANCE INFORMATION Am42BDS6408H Am29BDS640H 64 Megabit ( 16-Bit) Stacked MultiChip Package (MCP) Flash Memory and SRAM CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory, and 8 Mbit (512 K x 16-Bit) SRAM FLASH DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES Single 1.8 volt read, program and erase (1.65 to 1.95 volt) Manufactured on 0.13 µ ...
Page 4
... SRAM FEATURES Power dissipation — Operating typical — Standby: 2 µA CE1s# and CE2 Chip Select Power down features using CE1s# and CE2s Data retention supply voltage: 1.0 to 2.2 volt Byte data control: LB# (DQ7-DQ0), UB#s (DQ15-DQ8) Am42BDS6408H October 23, 2003 ...
Page 5
... AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electri- cally erases all bits within a sector simultaneously via Fowler-Nordheim tunnelling. The data is programmed using hot electron injection. Am42BDS6408H de WP# locks the IL 3 ...
Page 6
... Configuration Register ................................................................. 14 Reduced Wait-state Handshaking Option ....................................14 Simultaneous Read/Write Operations with Zero Latency ............ 14 Writing Commands/Command Sequences .................................. 14 Accelerated Program Operation ...................................................15 Table 3. Am42BDS6408H Boot Sector/Sector Block tion/Unprotection ...................................................................................16 Sector/Sector Block Protection and Unprotection ........................16 Sector Protection ..........................................................................16 Selecting a Sector Protection Mode .............................................16 Persistent Sector Protection ......................................................... 17 Persistent Protection Bit (PPB) ....................................................17 Persistent Protection Bit Lock (PPB Lock) ...
Page 7
... Figure 49. SRAM Write Cycle—WE# Control....................................... 82 Figure 50. SRAM Write Cycle—CE1#s Control.................................... 83 Figure 51. SRAM Write Cycle—UB#s and LB#s Control...................... 84 Erase and Programming Performance . . . . . . . 85 BGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . 85 Data Retention Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 86 TLB 089—89-ball Fine-Pitch Ball Grid Array (FBGA Package ............................................................................. 86 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 87 Am42BDS6408H = 1.8 V) ..................................... ...
Page 8
... Speed Options ending in “9” and “7” indicate the “standard handshaking” option. See the AC Characteristics section of this datasheet for full specifications – 1.65 1. IACC ) IACC ) ) ACC Am42BDS6408H Am42BDS6408H 66 MHz 54 MHz E8, E9 E3, E4 D8 87.5 87 ...
Page 9
... State CLK Control A21–A0 October 23, 2003 RDY Erase Voltage Generator PGM Voltage Generator Chip Enable Output Enable Logic Y-Decoder Timer X-Decoder Burst Address Counter Am42BDS6408H DQ15 – DQ0 Input/Output Buffers Data Latch Y-Gating Cell Matrix 7 ...
Page 10
... A21–A0 A21– Bank A Address Bank A X-Decoder Bank B Address Bank B X-Decoder Status Control X-Decoder Bank C Bank C Address X-Decoder Bank D Address Bank D Am42BDS6408H DQ15–DQ0 OE# DQ15–DQ0 DQ15–DQ0 DQ15–DQ0 DQ15–DQ0 October 23, 2003 ...
Page 11
... Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compro- mised if the package body is exposed to temperatures above 150°C for prolonged periods of time. Am42BDS6408H A10 Flash Only NC SRAM Only E10 NC F10 NC ...
Page 12
... WP# ACC LOGIC SYMBOL Am42BDS6408H High = device ignores address in- puts = Hardware write protect input disables program and erase func- tions in the two outermost sectors. Should for all other condi- IH tions. ...
Page 13
... WP Valid Combinations Package Marking Order Number Am42BDS6408HE8 M420000070 Am42BDS6408HE9 M420000071 Am42BDS6408HD8 M420000072 Am42BDS6408HD9 M420000073 I Am42BDS6408HE3 M420000074 Am42BDS6408HE4 M420000075 Am42BDS6408HD3 M420000076 Am42BDS6408HD4 M420000077 October 23, 2003 Tape and Reel Inches Inches TEMPERATURE RANGE ...
Page 14
... The IH Requirements for Synchronous (Burst) Read Operation The device is capable of continuous sequential burst operation and linear burst operation of a preset length. Am42BDS6408H Table 1 lists the device bus opera- CLK (See DQ15–0 RESET# Note) ...
Page 15
... CLK edge. Burst Suspend occurs when OE# is de-asserted. See Handshake Burst Suspend/Resume at an even address,” on page 57, Figure 19, “Reduced Wait-state Handshake Burst Suspend/Resume at an odd address,” on page 57, Figure 20, “Reduced Wait-state Am42BDS6408H Table 2. Burst Address Groups Group Size Group Address Ranges 8 words 0-7h, 8-Fh, 10-17h,... 16 words 0-Fh, 10-1Fh, 20-2Fh, ...
Page 16
... The device address space is divided into four banks: Banks B and C contain only 32 Kword sectors, while Banks A and D contain both 4 Kword boot sectors in addition to 32 Kword sectors. A Am42BDS6408H shows how read and write cycles may be when providing an address to the IH ...
Page 17
... In addition, the ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result . When ACC locks all sectors. ACC should for all other conditions. IH Am42BDS6408H . Note that the HH for operations other than HH 15 ...
Page 18
... Addresses for Protection/Unprotection,” on page 16 128 (4x32) Kwords 128 (4x32) Kwords Sector Protection 128 (4x32) Kwords The Am42BDS6408H features several levels of sector 128 (4x32) Kwords protection, which can disable both the program and 128 (4x32) Kwords erase operations in certain sectors or sector groups: ...
Page 19
... PPB Lock disables all program and erase commands to the Non-Volatile PPBs. In effect, the PPB Lock Bit locks the PPBs into their current state. The only way to clear the PPB Lock through a power cycle. System boot code can determine if any changes to the Am42BDS6408H 17 ...
Page 20
... Mode Locking Bit is set, the password is permanently set with no means to read, program, or erase it. The password is used to clear the PPB Lock bit. The Pass- word Unlock command must be written to the flash, along with a password. The flash device internally compares the given password with the pre-pro- Am42BDS6408H October 23, 2003 ...
Page 21
... The I in the “DC Characteristics” section on page 49 CC3 represents the standby current specification. Am42BDS6408H ) to be placed on the ID Figure 2, “In-System Sector Pro- ± 0 for read CE 19 ...
Page 22
... If RESET# is held Notes: 1. All protected sectors unprotected (If WP outermost boot sectors will remain protected). 2. All previously protected sectors are protected once again. (during READY Am42BDS6408H READY . IH “AC Characteristics” section on page 64 Figure 30, “Reset Tim- for the timing diagram. , output from the device is ...
Page 23
... Reset PLSCNT = 1 Increment PLSCNT No Yes PLSCNT = 1000? Yes Device failed Sector Unprotect Algorithm Figure 2. In-System Sector Protection/ Sector Unprotection Algorithms Am42BDS6408H START PLSCNT = 1 RESET Wait 1 µs No First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes No All sectors protected? ...
Page 24
... When ACC The following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V tions, or from system noise. Am42BDS6408H This IH ID Table 16, “Com- for command defini- , the four outermost sectors are IL , all sectors are locked ...
Page 25
... Table 6. CFI Query Identification String Query Unique ASCII string “QRY” Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists) Am42BDS6408H and OE Tables 6-9. To terminate reading Tables ...
Page 26
... Max. number of bytes in multi-byte write = 2 (00h = not supported) Number of Erase Block Regions within device Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) Erase Block Region 2 Information Erase Block Region 3 Information Erase Block Region 4 Information Am42BDS6408H N µs N µ s (00h = not supported ...
Page 27
... Dual Boot Device, 02h = Bottom Boot Device, 03h = Top Boot Device Program Suspend. 00h = not supported Bank Organization Number of banks Bank A Region Information Number of sectors in bank Bank B Region Information Number of sectors in bank Bank C Region Information Number of sectors in bank Bank D Region Information Number of sectors in bank Am42BDS6408H 25 ...
Page 28
... Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Am42BDS6408H Address Range 000000h-000FFFh 001000h-001FFFh 002000h-002FFFh 003000h-003FFFh 004000h-004FFFh 005000h-005FFFh 006000h-006FFFh 007000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh ...
Page 29
... Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Am42BDS6408H Address Range 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh ...
Page 30
... Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Am42BDS6408H Address Range 200000h-207FFFh 208000h-20FFFFh 210000h-217FFFh 218000h-21FFFFh 220000h-227FFFh 228000h-22FFFFh 230000h-237FFFh 238000h-23FFFFh 240000h-247FFFh 248000h-24FFFFh 250000h-257FFFh 258000h-25FFFFh 260000h-267FFFh 268000h-26FFFFh 270000h-277FFFh 278000h-27FFFFh 280000h-287FFFh 288000h-28FFFFh ...
Page 31
... Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords Am42BDS6408H Address Range 300000h-307FFFh 308000h-30FFFFh 310000h-317FFFh 318000h-31FFFFh 320000h-327FFFh 328000h-32FFFFh 330000h-337FFFh 338000h-33FFFFh 340000h-347FFFh 348000h-34FFFFh 350000h-357FFFh 358000h-35FFFFh 360000h-367FFFh 368000h-36FFFFh 370000h-377FFFh 378000h-37FFFFh 380000h-387FFFh 388000h-38FFFFh ...
Page 32
... The wait state command sequence instructs the device to set a particular number of clock cycles for the initial access in burst mode. The number of wait states that should be programmed into the device is directly related to the clock frequency. Am42BDS6408H Power-up/ Hardware Reset Asynchronous Read Mode Only ...
Page 33
... Typical initial access cycles may vary depending on system margin requirements. Standard Handshaking Option For optimal burst mode performance on devices with the standard handshaking option, the host system must set the appropriate number of wait states in the flash device depending on the clock frequency. Am42BDS6408H Handshaking Device Even Initial ...
Page 34
... RDY active with data, “0” for RDY active one clock cycle before valid data. In asyn- chronous mode, RDY is an open-drain output. Configuration Register Table 15 shows the address bits that determine the configuration register settings for various device func- tions. Am42BDS6408H Address Bits A16 A15 ...
Page 35
... Read com- mands to other banks will return data from the array. The following table describes the address require- ments for the various autoselect functions, and the resulting data. BA represents the bank address, and Am42BDS6408H ...
Page 36
... The first cycle must contain the bank address and the data 90h. The second cycle need only contain the data 00h. The bank then returns to the read mode. Am42BDS6408H Table 16, “Command Defini- shows the address and data require- “Write Operation Status” ...
Page 37
... Any sector erase address and command following the exceeded time-out may or may not be accepted recommended that processor interrupts be disabled during this time to ensure all commands are accepted. Am42BDS6408H Table 16, shows the address for Table 16, ...
Page 38
... Command Sequence” section on page 33 for details. To resume the sector erase operation, the system must write the Erase Resume command. The bank address of the erase-suspended bank is required when writing this command. Further writes of the Resume command Am42BDS6408H for for more October 23, 2003 ...
Page 39
... Mode Locking Bit, the device is forced to remain in the Persistent Sector Protection mode of operation, once this bit is set. Exiting the Persistent Protection Mode Locking Bit Program command is accomplished by writing the Read/Reset command. When the Persis- tent Sector Protection Mode Locking Bit is undergoing programming, Simultaneous Operation is disabled. Am42BDS6408H 37 ...
Page 40
... ALL PPB Erase command will not execute and the command will time-out without erasing the PPBs. After erasing the PPBs, two additional cycles are needed to determine whether the PPB has been erased with margin. If the PPBs has been erased with- Am42BDS6408H October 23, 2003 ...
Page 41
... The programming of the PPB Lock Bit for a given sec- tor can be verified by writing a PPB Lock Bit status ver- ify command to the device. DYB Status Command The programming of the DYB for a given sector can be verified by writing a DYB Status command to the de- vice. Am42BDS6408H 39 ...
Page 42
... AA 2AA 55 555 90 555 AA 2AA 55 555 60 555 AA 2AA 55 555 38 555 AA 2AA 55 555 C8 555 AA 2AA 55 555 28 Am42BDS6408H Fourth Fifth Sixth Data Addr Data Addr Data Addr Data (BA) 0001 X00 (BA) (BA) (BA) 227E 221E 2201 X0E X0F X01 (SA) (Note 10) X02 (BA) (Note 11) X03 PA Data 555 AA ...
Page 43
... Standard Handshake), DQ4 - DQ0 = 0 12. The Unlock Bypass command sequence is required prior to this command sequence. 13. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode. Am42BDS6408H Fourth Fifth Sixth Data Addr Data Addr Data Addr Data ...
Page 44
... The entire four bus-cycle sequence must be entered for each portion of the password. 24. Before issuing the erase command, all PPBs should be programmed in order to prevent over-erasure of PPBs. 25. In the fourth cycle, 01h indicates PPB set; 00h indicates PPB not set. Am42BDS6408H October 23, 2003 ...
Page 45
... During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Figure 6. Data# Polling Algorithm Am42BDS6408H shows Figure 6, “Data# shows the Data# Polling in the AC ...
Page 46
... Embedded Algorithm),” on page 72 timing diagram), and Table 17, “DQ6 and DQ2 Indica- tions,” on page 46. Toggle Bit I on DQ6 requires either OE de-asserted and reasserted to show the change in state. Am42BDS6408H Figure 7, 45, “DQ6: Toggle Bit I” (toggle bit October 23, 2003 ...
Page 47
... Bit Algorithm,” on page 45, “DQ6: Toggle Bit I” “ (During Embedded Algorithm),” on page Table 17, “DQ6 and DQ2 Indications,” on page PASS Am42BDS6408H Figure 7, 72, and 46. 45 ...
Page 48
... DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the Am42BDS6408H and DQ2 does not toggle. also toggles. ...
Page 49
... Table 18 shows the status of DQ3 relative to the other status bits. Table 18. Write Operation Status DQ7 (Note 2) DQ6 (Note 1) DQ7# Toggle 0 Toggle 1 No toggle Data Data DQ7# Toggle Am42BDS6408H DQ5 DQ2 RDY (Note DQ3 (Note N/A No toggle Toggle 0 High 0 N/A Toggle ...
Page 50
... +0.8 V –0 0 –2 2.0 V for +2 +0.5 V 1.0 V > 100mV CC IO Am42BDS6408H Figure 8. Maximum Negative Overshoot Waveform Figure 9. Maximum Positive Overshoot Waveform October 23, 2003 ...
Page 51
... min I = –100 µ min max ns. Typical sleep mode current is equal to I ACC and V currents. ACC CC Am42BDS6408H Min Typ Max Unit ±1 µA ±1 µ 15 200 µA 0.2 10 µA TBD TBD mA ...
Page 52
... –0 CE1#s ≥ V – 0.2 V, CE2 ≥ – 0.2 V (CE1#s controlled) or CE2 ≤ 0.2 V (CE2s controlled), CIOs = Other input = ° C. Not 100% tested. A Am42BDS6408H Min Typ Max Unit –1.0 1.0 µA –1.0 1.0 µ 0 ...
Page 53
... Output timing measurement reference levels INPUTS Steady Changing from Changing from Does Not Apply Center Line is High Impedance State (High Input Measurement Level IO Am42BDS6408H Table 19. Test Specifications All Speed Options 0.0– OUTPUTS ...
Page 54
... Setup Time VCS Setup Time VIOS IO t RESET# Low Hold Time RSTH RESET Test Setup Min Min Min t VCS t VIOS t RSTH Figure 12. V Power-up Diagram CC Am42BDS6408H Speed Unit 50 µs 50 µs 50 µs October 23, 2003 ...
Page 55
... Notes: 1. Addresses are latched on the first of either the active edge of CLK or the rising edge of AVD#. 2. Please contact AMD for availability of V October 23, 2003 1 1.5 V devices. IO Am42BDS6408H E6, E7, D6, D7, E8, E9 D8, D9 (66 MHz) (54 MHz) Max 56 69 Max 71 87 ...
Page 56
... IACC t ACC cycles for initial access shown AVD t BDH t Da IACC t ACC t t RACC OE Am42BDS6408H t CEZ 7 t BDH t BACC OEZ t RACC Hi-Z t RDYS t CEZ t BACC Hi OEZ Hi-Z t RDYS ...
Page 57
... Figure 16. 8-word Linear Burst with Wrap Around October 23, 2003 cycles for initial access shown IACC t ACC IACC t ACC t RACC t RDYS Am42BDS6408H t CEZ 7 t BDH t BACC OEZ t RACC t RDYS t BDH t BACC Hi-Z ...
Page 58
... A18=0; device will output RDY one cycle before valid data. Figure 17. Linear Burst with RDY Set One Cycle Before Data wait cycles for initial access shown IACC t ACC t RACC RDYS Am42BDS6408H t CEZ t BDH t BACC OEZ October 23, 2003 Hi-Z Hi-Z ...
Page 59
... Data D(23) RDY t RACC Note: Figure is for any odd address other than 3Fh (or multiple thereof). Figure 19. Reduced Wait-state Handshake Burst Suspend/Resume at an odd address October 23, 2003 Resume x x+2 x+3 x+4 x+1 t OES t CKA D(20) D(21) D(22) t RACC Resume x x+2 x+3 x+4 x+1 t OES t CKA D(23) D(24) D(25) t RACC Am42BDS6408H x+6 x+7 x+8 x+5 D(23) D(23) D(23) D(24) x+6 x+7 x+8 x+5 D(25) D(25) D(26) D(27) 57 ...
Page 60
... AVD# t OES Addresses OE# t CKZ Data D(3F) RDY t RACC t RACC Figure 21. Reduced Wait-state Handshake Burst Suspend/Resume at address 3Fh (or offset from 3Fh Resume x+1 x+2 x+3 x OES t CKA D(3E) D(3F) D(3F) D(3F) t RACC Resume x+1 x+2 x+3 x OES t CKA D(3F) D(3F) D(3F) D(40) t RACC a multiple of 64) Am42BDS6408H x+5 x+7 x+8 x+9 x+6 D(41) D(41) D(41) D(40) D(41) D(42) x+5 x+7 x+8 x+9 x+6 D(41) D(41) D(42) D(41) D(43) D(41) October 23, 2003 x+10 x+10 ...
Page 61
... Figure 23. Standard Handshake Burst Suspend at or after Inital Access October 23, 2003 Resume Suspend x OES OES t CKA D(n) t RACC D(n) t RACC Suspend OES OES t CKA t CKZ D(n) t RACC t RACC D(n) D(n+1) t RACC Am42BDS6408H x+2 x+3 x+4 x+6 x+7 x+5 D(n+2) D(n+1) 3F D(3F) D(40) 3F D(n+1) D(n+2) D(n+3) D(n+4) D(n+5) D(n+6) Resume x 9 x+1 x+2 x+3 t OES t CKA D(n) D(n+1) t RACC D(n+2) D(n+ RACC RACC x+8 59 ...
Page 62
... Suspend OES OES t CKA D(3F) D(3D) D(3E RACC RACC Suspend OES t CKZ D(3E RACC RACC D(3F RACC RACC Am42BDS6408H Resume x x+2 x+1 x+4 x+3 t OES t CKA t CKZ D(3F) D(3F) D(3F) t RACC Resume x x+1 x+2 x+3 x+4 x+5 t OES t CKA D(40) D(3F) D(41) D(42) D(3E) t RACC D(3F) D(40) D(41) D(42) D(43) t ...
Page 63
... Figure 27. Read Cycle for Continuous Suspend October 23, 2003 Suspend OES t CKZ D(3F) D(3E) t RACC t RACC D(3F) D(40 RACC RACC Suspend Resume x OES OES t CKA D(n) RCC Am42BDS6408H Resume x x+1 x+2 x+3 x+4 x+5 x+6 t OES t CKA D(40) D(3F) D(41) D(42) t RACC D(41) D(42) D(43) D(40) t RACC x+2 x+3 x+4 x+6 x+7 x+5 t RCC D(n) D(n+2) D(3F) D(n+1) D(3F) D(3F) t RACC ??? ...
Page 64
... CAS Notes: 1. Asynchronous Access Time is from the last of either stable addresses or the falling edge of AVD#. 2. Not 100% tested 1 Read Toggle and Data# Polling Am42BDS6408H E3, E4, D6, D7, E8, E9 D8, D9 (66 MHz) (54 MHz) Unit Max 50 TBD ns Max ...
Page 65
... OE# WE# Data Addresses AVD# Note Read Address Read Data. October 23, 2003 OEH ACC AAVDH CAS t AVDP t AAVDS OEH ACC RA Figure 29. Asynchronous Mode Read Am42BDS6408H t OEZ Valid RD t OEZ Valid RD 63 ...
Page 66
... RESET Description Ready Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms t Ready t RP Figure 30. Reset Timings Am42BDS6408H All Speed Options Unit Max 20 µs Max 500 ns Min 500 ns Min 200 ns Min 20 µ ...
Page 67
... WE# or the active edge of CLK. 4. See the “Erase and Programming Performance” section for more information. 5. Does not include the preprogramming time. October 23, 2003 1 Synchronous Asynchronous Synchronous Asynchronous Am42BDS6408H E6, E7, D6, D7, E8, E9 D8, D9 (66 MHz) (54 MHz) Unit Min 50 55 ...
Page 68
... The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Configuration Register. Figure 31. Asynchronous Program Operation Timings: AVD# Latched Addresses WPH t WC Am42BDS6408H Read Status Data Complete Progress t WHWH1 October 23, 2003 ...
Page 69
... The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Configuration Register. Figure 32. Asynchronous Program Operation Timings: WE# Latched Addresses October 23, 2003 AVHW t AVDP WPH t WC Am42BDS6408H Read Status Data Complete Progress t WHWH1 67 ...
Page 70
... The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register. The Configuration Register must be set to the Synchronous Read Mode. Figure 33. Synchronous Program Operation Timings: WE# Latched Addresses ACH PA A0h WPH t WC Am42BDS6408H Read Status Data Complete Progress t WHWH1 October 23, 2003 ...
Page 71
... The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register. The Configuration Register must be set to the Synchronous Read Mode. Figure 34. Synchronous Program Operation Timings: CLK Latched Addresses October 23, 2003 A0h WPH t WC Am42BDS6408H Read Status Data Complete Progress t WHWH1 69 ...
Page 72
... Address bits A21–A12 are don’t cares during unlock cycles in the command sequence 555h for 10h for chip erase chip erase 30h WPH t WC Am42BDS6408H Read Status Data Complete Progress t WHWH2 October 23, 2003 ...
Page 73
... Data Don't Care OE# 1 µs V ACC Note: Use setup and hold times from conventional program operation. Figure 36. Accelerated Unlock Bypass Programming Timing October 23, 2003 A0h Don't Care t VIDS t VID Am42BDS6408H PA PD Don't Care 71 ...
Page 74
... While in Asynchronous mode, RDY will be low while the device is in embedded erase or programming mode. Figure 38. Toggle Bit Timings (During Embedded Algorithm CEZ t OEZ VA Status Data VA Status Data Am42BDS6408H Status Data t CEZ t OEZ Status Data October 23, 2003 ...
Page 75
... Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6. October 23, 2003 IACC Status Data Enter Erase Suspend Program Erase Suspend Read Program Figure 40. DQ2 vs. DQ6 Am42BDS6408H t IACC Status Data Erase Resume Erase Erase Suspend Complete Read Erase 73 ...
Page 76
... VIDR CE# WE# RDY Figure 41. Temporary Sector Unprotect Timing Diagram Min Min Min Min Program or Erase Command Sequence t RSP Am42BDS6408H All Speed Options Unit 500 ns 250 ns 4 µs 4 µ VIDR ...
Page 77
... For sector protect For sector unprotect Figure 42. Sector/Sector Block Protect and October 23, 2003 Valid* 60h Sector Protect: 150 µs Sector Unprotect Unprotect Timing Diagram Am42BDS6408H Valid* Valid* Verify 40h Status 75 ...
Page 78
... Figure 43. Latency with Boundary Crossing C62 C63 C63 C63 RACC RACC latency t t RACC RACC latency D62 D63 Am42BDS6408H C64 C65 C66 C67 D64 D65 D66 D67 October 23, 2003 ...
Page 79
... Figure 44. Latency with Boundary Crossing October 23, 2003 C62 C63 C63 C63 RACC latency t t RACC RACC latency D61 D62 D63 into Program/Erase Bank Am42BDS6408H C64 40 t RACC Invalid Read Status 77 ...
Page 80
... total number of clock cycles following AVD# falling edge number of clock cycles programmed Am42BDS6408H D0 D1 Rising edge of next clock cycle following last wait state triggers next burst data October 23, 2003 ...
Page 81
... October 23, 2003 Read status (at least two cycles) in same bank and/or array data from other bank OEH t OEZ t ACC t t OEH SR Am42BDS6408H Begin another write or program command sequence GHWL RD AAh 555h 79 ...
Page 82
... Address Data Out Previous Data Valid Note: CE1 CE2s = WE Figure 47. SRAM Read Cycle—Address Controlled UB#s and/or LB Am42BDS6408H E6, E7, E8, E9, Unit D6, D7 D8, D9 Min Max Max Max ...
Page 83
... At any given temperature and voltage condition, t interconnection. October 23, 2003 CO1 t CO2 OLZ t BLZ t LZ Data Valid Figure 48. SRAM Read Cycle (Max.) is less than t (Min.) both for a given device and from device to device HZ LZ Am42BDS6408H OHZ 81 ...
Page 84
... Note (See Note 3) High-Z t WHZ Data Undefined applied in case a write ends as CE1#s or WE# going high low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when Am42BDS6408H E6, E7, E8, E9, D6, D7 D8, D9 Min 55 70 Min 45 60 ...
Page 85
... (See Note 5) High-Z applied in case a write ends as CE1#s or WE# going high low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when Am42BDS6408H t (See Note Data Valid High-Z is measured from the beginning of write ...
Page 86
... AS t (See Note 4) WP (See Note 5) High-Z applied in case a write ends as CE1#s or WE# going high low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when Am42BDS6408H t (See Note Data Valid High-Z is measured from the beginning of write ...
Page 87
... C, 1 1.65 V, 1,000,000 cycles. CC Test Setup OUT V IN Test Conditions 150°C 125°C Am42BDS6408H Unit Comments s Excludes 00h programming prior to erasure (Note 4) s Excludes system level µs overhead (Note 5) µs Excludes system level s overhead (Note million cycles. Additionally, ...
Page 88
... OUTER ROW 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. Am42BDS6408H ...
Page 89
... Copyright © 2003 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. October 23, 2003 Am42BDS6408H 87 ...
Page 90
Sales Offices and Representatives North America ALABAMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...