am42bds6408h Meet Spansion Inc., am42bds6408h Datasheet - Page 34

• Manufacturer Part Number: am42bds6408h
• Description: Cmos 1.8 Volt-only Simultaneous Read/write, Burst Mode Flash Memory, And 8 Mbit 512 K X 16-bit Sram
• Manufacturer: Meet Spansion Inc.

Table 13
(wait states) for various conditions with A14-A12 set to
101.
* In the 8-, 16- and 32-word burst read modes, the address
pointer does not cross 64-word boundaries (addresses
which are multiples of 3Fh).
The autoselect function allows the host system to
determine whether the flash device is enabled for
h a nd sh a kin g . Se e t he
Sequence” section on page 33
Read Mode Configuration
The device supports four different read modes: contin-
uous mode, and 8, 16, and 32 word linear wrap around
modes. A continuous sequence begins at the starting
address and advances the address pointer until the
burst operation is complete. If the highest address in
the device is reached during the continuous burst read
mode, the address pointer wraps around to the lowest
address.
For example, an eight-word linear read with wrap
around begins on the starting address written to the
device and then advances to the next 8 word boundary.
The address pointer then returns to the 1st word after
the previous eight word boundary, wrapping through
the starting location. The sixteen- and thirty-two linear
wrap around modes operate in a fashion similar to the
eight-word mode.
32
Conditions at Address
Initial address
Initial address is 3E or 3Fh (or
offset from these addresses by
a multiple of 64) and is at
boundary crossing*
Table 13. Wait States for Standard Handshaking
describes the typical number of clock cycles
“ Au t o se le ct C om m an d
Cycles after AVD# Low
for more information.
A D V A N C E
Typical No. of Clock
7
7
Am42BDS6408H
I N F O R M A T I O N
Table 14
four read modes.
Note: Upon power-up or hardware reset the default setting is
continuous.
Burst Active Clock Edge Configuration
By default, the device will deliver data on the rising
edge of the clock after the initial synchronous access
time. Subsequent outputs will also be on the following
rising edges, barring any delays. The device can be set
so that the falling clock edge is active for all synchro-
nous accesses. Address bit A17 determines this set-
ting; “1” for rising active, “0” for falling active.
RDY Configuration
By default, the device is set so that the RDY pin will
output V
The device can be set so that RDY goes active one
data cycle before active data. Address bit A18 deter-
mines this setting; “1” for RDY active with data, “0” for
RDY active one clock cycle before valid data. In asyn-
chronous mode, RDY is an open-drain output.
Configuration Register
Table 15
configuration register settings for various device func-
tions.
Burst Modes
Continuous
8-word linear wrap around
16-word linear wrap around
32-word linear wrap around
OH
shows the address bits and settings for the
shows the address bits that determine the
Table 14. Read Mode Settings
whenever there is valid data on the outputs.
A16
0
0
1
1
October 23, 2003
Address Bits
A15
0
1
0
1