am42bds6408h Meet Spansion Inc., am42bds6408h Datasheet - Page 16

• Manufacturer Part Number: am42bds6408h
• Description: Cmos 1.8 Volt-only Simultaneous Read/write, Burst Mode Flash Memory, And 8 Mbit 512 K X 16-bit Sram
• Manufacturer: Meet Spansion Inc.

Handshake Burst Suspend/Resume at address 3Eh (or
offset from 3Eh),” on page 58, Figure 21, “Reduced
Wait-state Handshake Burst Suspend/Resume at
address 3Fh (or offset from 3Fh by a multiple of 64),” on
page 58, Figure 22, “Standard Handshake Burst
Suspend prior to Initial Access,” on page 59, Figure 23,
“Standard Handshake Burst Suspend at or after Inital
Access,” on page 59, Figure 24, “Standard Handshake
Burst Suspend at address 3Fh (starting address 3Dh
or earlier),” on page 60, Figure 25, “Standard Hand-
shake Burst Suspend at address 3Eh/3Fh (without a
valid Initial Access),” on page 60,
dard Handshake Burst Suspend at address 3Eh/3Fh
(with 1 Access CLK),” on page 61.
Burst plus Burst Suspend should not last longer than
t
address boundary. To resume the burst access, OE#
must be re-asserted. The next active CLK edge will
resume the burst sequence where it had been sus-
pended.
Suspend,” on page 61.
The RDY pin is only controlled by CE#. RDY will remain
active and is not placed into a high-impedance state
when OE# is de-asserted.
Configuration Register
The device uses a configuration register to set the
various burst parameters: number of wait states, burst
read mode, active clock edge, RDY configuration, and
synchronous mode active.
Reduced Wait-state Handshaking Option
The device can be equipped with a reduced wait-state
handshaking feature that allows the host system to
simply monitor the RDY signal from the device to deter-
mine when the initial word of burst data is ready to be
read. The host system should use the programmable
wait state configuration to set the number of wait states
for optimal burst mode operation. The initial word of
burst data is indicated by the rising edge of RDY after
OE# goes low.
The presence of the reduced wait-state handshaking
feature may be verified by writing the autoselect
command sequence to the device. See “Autoselect
Command Sequence” for details.
For optimal burst mode performance on devices
without the reduced wait-state handshaking option, the
host system must set the appropriate number of wait
states in the flash device depending on clock frequency
and the presence of a boundary crossing. See
Configuration Register Command Sequence” section
on page 30
will automatically delay RDY and data by one additional
clock cycle when the starting address is odd.
14
RCC
without re-latching an address or crossing an
See, Figure 27, “Read Cycle for Continuous
section for more information. The device
A D V A N C E
and
Figure 26, “Stan-
Am42BDS6408H
“Set
I N F O R M A T I O N
The autoselect function allows the host system to
determine whether the flash device is enabled for
reduced wait-state handshaking. See the “Autoselect
Command Sequence” section for more information.
Simultaneous Read/Write Operations with
Zero Latency
This device is capable of reading data from one bank of
memory while programming or erasing in another bank
of memory. An erase operation may also be suspended
to read from or program to another location within the
sa me bank (except the sector being erased).
Figure 46, “Back-to-Back Read/Write Cycle Timings,”
on page 79
initiated for simultaneous operation with zero latency.
R e f e r t o t h e D C C h a r a c t e r i s t i c s t a b l e f o r
read-while-program and read-while-erase current
specifications.
Writing Commands/Command Sequences
The device has the capability of performing an asyn-
chronous or synchronous write operation. While the
device is configured in Asynchronous read it is able to
perform Asynchronous write operations only. CLK is
ignored in the Asynchronous programming mode.
When in the Synchronous read mode configuration, the
device is able to perform both Asynchronous and Syn-
chronous write operations. CLK and WE# address
latch is supported in the Synchronous programming
mode. During a synchronous write operation, to write a
command or command sequence (which includes pro-
gramming data to the device and erasing sectors of
memory), the system must drive AVD# and CE# to V
and OE# to V
device, and drive WE# and CE# to V
when writing commands or data. During an asynchro-
nous write operation, the system must drive CE# and
WE# to V
command, and data. Addresses are latched on the last
falling edge of WE# or CE#, while data is latched on the
1st rising edge of WE# or CE#. The asynchronous and
synchronous programing operation is independent of
the Set Device Read Mode bit in the Configuration
Register (see
page
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are
required to program a word, instead of four.
An erase operation can erase one sector, multiple sec-
tors, or the entire device.
Table,” on page 26
each sector occupies. The device address space is
divided into four banks: Banks B and C contain only 32
Kword sectors, while Banks A and D contain both 4
Kword boot sectors in addition to 32 Kword sectors. A
33).
IL
and OE# to V
shows how read and write cycles may be
IH
Table 15, “Configuration Register,” on
when providing an address to the
indicates the address space that
IH
when providing an address,
Table 10, “Sector Address
IL
October 23, 2003
, and OE# to V
IL
IH
,