am42bds6408h Meet Spansion Inc., am42bds6408h Datasheet - Page 43

• Manufacturer Part Number: am42bds6408h
• Description: Cmos 1.8 Volt-only Simultaneous Read/write, Burst Mode Flash Memory, And 8 Mbit 512 K X 16-bit Sram
• Manufacturer: Meet Spansion Inc.

Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses
latch on the rising edge of the AVD# pulse or active edge of CLK which
ever comes first.
PD = Data to be programmed at location PA. Data latches on the rising
edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A21–A12 uniquely select any sector.
BA = Address of the bank (A21, A20, A19) that is being switched to
autoselect mode, is in bypass mode, or is being erased.
SLA = Address of the sector to be locked. Set sector address (SA) and
either A6 = 1 for unlocked or A6 = 0 for locked.
CR = Configuration Register address bits A19–A12.
Notes:
1.
2. All values are in hexadecimal.
3. Except for the following, all bus cycles are write cycle: read cycle,
4. Data bits DQ15–DQ8 are don’t care in command sequences,
5. Unless otherwise noted, address bits A21–A12 are don’t cares.
6. Writing incorrect address and data values or writing them in the
7. No unlock or command cycles required when bank is reading
8. The Reset command is required to return to reading array data
October 23, 2003
PPB
Command
s
PPB Lock
Bit
DYB
Password Protection Mode Locking
Bit Program (Notes 18, 19, 21)
Persistent Protection Mode Locking
Bit Program (Notes 18, 19, 21)
Password Protection Mode Locking
Bit Read (Notes 18, 19, 21)
Persistent Protection Mode Locking
Bit Read (Notes 18, 19, 21)
See Table 1 for description of bus operations.
fourth through sixth cycles of the Autoselect commands, fourth
cycle of the configuration register verify and password verify
commands, and any cycle reading at RD(0) and RD(1).
except for RD, PD, WD, PWD, and PD3-PD0.
improper sequence may place the device in an unknown state.
The system must write the reset command to return the device to
reading array data.
array data.
(or to the erase-suspend-read mode if previously in Erase
Command Sequence
PPB Program (Notes 18,
19, 21)
All PPB Erase (Notes
18, 19, 22, 24)
PPB Status (Note 25)
PPB Lock Bit Set
PPB Lock Bit Status
(Note 19)
DYB Write
DYB Erase
DYB Status
(Note 1)
6
6
4
3
4
4
4
4
6
6
4
4
A D V A N C E
Addr Data Addr Data Addr Data Addr
555
555
555
555
555
555
555
555
555
555
555
555
First
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
Second
Am42BDS6408H
55
55
55
55
55
55
55
55
55
55
55
55
I N F O R M A T I O N
(BA)
(BA)
(BA)
555
555
555
555
555
555
555
555
555
555
555
555
OW = Address (A7–A0) is (00011010).
PD3–PD0 = Password Data. PD3–PD0 present four 16 bit
combinations that represent the 64-bit Password
PWA = Password Address. Address bits A1 and A0 are used to select
each 16-bit portion of the 64-bit entity.
PWD = Password Data.
PL = Address (A7-A0) is (00001010)
RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 1, if
unprotected, DQ0 = 0.
RD(1) = DQ1 protection indicator bit. If protected, DQ1 = 1, if
unprotected, DQ1 = 0.
SL = Address (A7-A0) is (00010010)
WD= Write Data. See “Configuration Register” definition for specific
write data
WP = Address (A7-A0) is (00000010)
9. The fourth cycle of the autoselect command sequence is a read
10. The data is 0000h for an unlocked sector and 0001h for a locked
11. DQ15 - DQ8 = 0, DQ7: Factory Lock Bit (1 = Locked, 0 = Not
12. The Unlock Bypass command sequence is required prior to this
13. The Unlock Bypass Reset command is required to return to
Third
Suspend) when a bank is in the autoselect mode, or if DQ5 goes
high (while the bank is providing status information) or performing
sector lock/unlock.
cycle. The system must provide the bank address. See the
Autoselect Command Sequence section for more information.
sector
Locked), DQ6: Customer Lock Bit (1 = Locked, 0 = Not Locked),
DQ5: Handshake Bit (1 = Reduced wait-state Handshake, 0 =
Standard Handshake), DQ4 - DQ0 = 0
command sequence.
reading array data when the bank is in the unlock bypass mode.
Bus Cycles (Notes 1–6)
60
60
90
78
58
48
48
58
60
60
60
60
+ WP
(SA)
(SA)
X02
WP
SA
SA
SA
SA
PL
SL
PL
SL
Fourth
Data
RD
RD
RD
RD
RD
(0)
(1)
X1
X0
(0)
(0)
(0)
68
60
68
68
Addr Data Addr Data Addr Data
+ WP
(SA)
WP
PL
SL
Fifth
48
40
48
48
XX
XX
PL
SL
Sixth
RD
RD
RD
RD
(0)
(0)
(0)
(0)
Seventh
41