am42bds6408h Meet Spansion Inc., am42bds6408h Datasheet - Page 36

• Manufacturer Part Number: am42bds6408h
• Description: Cmos 1.8 Volt-only Simultaneous Read/write, Burst Mode Flash Memory, And 8 Mbit 512 K X 16-bit Sram
• Manufacturer: Meet Spansion Inc.

SA represents the sector address. The device ID is
read in three cycles.
The system must write the reset command to return to
the read mode (or erase-suspend-read mode if the
bank was previously in Erase Suspend).
Enter SecSi™ Sector/Exit SecSi Sector
Command Sequence
The SecSi Sector region provides a secured data area
containing a random, eight word electronic serial num-
ber (ESN). The system can access the SecSi Sector
region by issuing the three-cycle Enter SecSi Sector
command sequence. The device continues to access
the SecSi Sector region until the system issues the
four-cycle Exit SecSi Sector command sequence. The
Exit SecSi Sector command sequence returns the de-
vice to normal operation. The SecSi Sector is not ac-
cessible when the device is executing an Embedded
Program or embedded Erase algorithm.
“Command Definitions,” on page 40
and data requirements for both command sequences.
Program Command Sequence
Programming is a four-bus-cycle operation. The
program command sequence is initiated by writing two
unlock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program
algorithm. The system is not required to provide further
controls or timings. The device automatically provides
34
Manufacturer
ID
Device ID,
Word 1
Device ID,
Word 2
Device ID,
Word 3
Sector
Protection
Verification
Indicator Bits
Description
(BA) + 0Eh
(BA) + 0Fh
(BA) + 00h
(BA) + 01h
(SA) + 02h
(BA) + 03h
Address
1 = Locked, 0 = Not Locked
1 = Locked, 0 = Not Locked
0 = Standard Handshake
DQ6: Customer Lock Bit
1 = Reduced Wait-state
DQ7: Factory Lock Bit
DQ5: Handshake Bit
A D V A N C E
DQ15 - DQ8 = 0
0000 (unlocked)
0001 (locked),
Handshake,
Read Data
shows the address
227Eh
221Eh
0001h
2201h
Table 16,
Am42BDS6408H
I N F O R M A T I O N
internally generated program pulses and verifies the
programmed cell margin.
tions,” on page 40
ments for the program command sequence.
When the Embedded Program algorithm is complete,
that bank then returns to the read mode and addresses
are no longer latched. The system can determine the
status of the program operation by monitoring DQ7 or
DQ6/DQ2. Refer to the
section on page 43
Any commands written to the device during the
Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program
operation. The program command sequence should be
reinitiated once that bank has returned to the read
mode, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed from
“0” back to a “1.” Attempting to do so may cause that
bank to set DQ5 = 1, or cause the DQ7 and DQ6 status
bit to indicate the operation was successful. However,
a succeeding read will show that the data is still “0.”
Only erase operations can convert a “0” to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to prima-
rily program to a bank faster than using the standard
program command sequence. The unlock bypass
command sequence is initiated by first writing two
unlock cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h. The
device then enters the unlock bypass mode. A
two-cycle unlock bypass program command sequence
is all that is required to program in this mode. The first
cycle in this sequence contains the unlock bypass
program command, A0h; the second cycle contains the
program address and data. Additional data is pro-
grammed in the same manner. This mode dispenses
with the initial two unlock cycles required in the stan-
dard program command sequence, resulting in faster
total programming time. The host system may also ini-
tiate the chip erase and sector erase sequences in the
unlock bypass mode. The erase command sequences
are four cycles in length instead of six cycles.
“Command Definitions,” on page 40
ments for the unlock bypass command sequences.
During the unlock bypass mode, only the Read, Unlock
Bypass Program, Unlock Bypass Sector Erase, Unlock
Bypass Chip Erase, and Unlock Bypass Reset com-
mands are valid. To exit the unlock bypass mode, the
system must issue the two-cycle unlock bypass reset
command sequence. The first cycle must contain the
bank address and the data 90h. The second cycle
need only contain the data 00h. The bank then returns
to the read mode.
shows the address and data require-
for information on these status bits.
Table 16, “Command Defini-
“Write Operation Status”
shows the require-
October 23, 2003
Table 16,