am42bds6408h Meet Spansion Inc., am42bds6408h Datasheet - Page 12

• Manufacturer Part Number: am42bds6408h
• Description: Cmos 1.8 Volt-only Simultaneous Read/write, Burst Mode Flash Memory, And 8 Mbit 512 K X 16-bit Sram
• Manufacturer: Meet Spansion Inc.

PIN DESCRIPTION
A18–A0
A21–A19
DQ15–DQ0
CE#f
CE1#s
CE2s
OE#
WE#
UB#s
LB#s
RESET#
V
V
V
V
V
NC
RDY
CLK
AVD#
10
CC
IO
CC
SSIO
SS
f
f
s
f
= 19 Address Inputs (Common)
= 3 Address Inputs (Flash)
= Chip Enable (Flash)
= Write Enable (Common)
= Lower Byte Control (SRAM)
= Hardware Reset Pin, Active Low
= 16 Data Inputs/Outputs (Common)
= Chip Enable 1 (SRAM)
= Chip Enable 2 (SRAM)
= Output Enable (Common)
= Upper Byte Control (SRAM)
= Flash 1.8 volt-only single power
= Input & Output Buffer Power Supply
= SRAM Power Supply
= Output Buffer Ground
= Device Ground (Common)
= Pin Not Connected Internally
= Ready output; indicates the status of
= CLK is not required in asynchronous
= Address Valid input. Indicates to de-
supply (see Product Selector Guide
for speed options and voltage supply
tolerances)
must be tied to V
the Burst read. Low = data not valid
at expected time. High = data valid.
mode. In burst mode, after the initial
word is output, subsequent active
edges of CLK increment the internal
address counter.
vice that the valid address is present
on the address inputs (A21–A0).
Low = for asynchronous mode, indi-
cates valid address; for burst mode,
causes starting address to be
latched.
A D V A N C E
CC
.
Am42BDS6408H
I N F O R M A T I O N
WP#
ACC
LOGIC SYMBOL
19
A21–A19
CE#f
CE1#s
CE2s
OE#
WE#
WP#
RESET#
UB#s
LB#s
ACC
AVD#
A18–A0
CLK
= Hardware write protect input. At V
= At V
High = device ignores address in-
puts
disables program and erase func-
tions in the two outermost sectors.
Should be at V
tions.
automatically places device in un-
lock bypass mode. At V
sectors. Should be at V
other conditions.
ID
DQ15–DQ0
, accelerates programming;
RDY
IH
for all other condi-
October 23, 2003
16
IH
IL
, locks all
for all
IL
,