am42bds6408h Meet Spansion Inc., am42bds6408h Datasheet - Page 3

• Manufacturer Part Number: am42bds6408h
• Description: Cmos 1.8 Volt-only Simultaneous Read/write, Burst Mode Flash Memory, And 8 Mbit 512 K X 16-bit Sram
• Manufacturer: Meet Spansion Inc.

Am42BDS6408H
Am29BDS640H 64 Megabit (4 M x 16-Bit)
Stacked MultiChip Package (MCP) Flash Memory and SRAM
CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash
Memory, and 8 Mbit (512 K x 16-Bit) SRAM
FLASH DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. Do not design in this product without contacting the factory. AMD re-
serves the right to change or discontinue work on this proposed product without notice.
Single 1.8 volt read, program and erase (1.65 to 1.95
volt)
Manufactured on 0.13 µm process technology
VersatileIO™ (V
— Device generates data output voltages and tolerates
— 1.8V compatible I/O signals
— Contact factory for availability of 1.5V compatible I/O
Simultaneous Read/Write operation
— Data can be continuously read from one bank while
— Zero latency between read and write operations
— Four bank architecture: 8Mb/24Mb/24Mb/8Mb
Programable Burst Interface
— 2 Modes of Burst Read Operation
— Linear Burst: 8, 16, and 32 words with
— Continuous Sequential Burst
SecSi
— Up to 128 words accessible through a command
— Up to 64 factory-locked words
— Up to 64 customer-lockable words
Sector Architecture
— Sixteen 4 Kword sectors and one hundred twenty-six
— Banks A and D each contain eight 4 Kword sectors
— Sixteen 4 Kword boot sectors: eight at the top of the
Minimum 1 million erase cycle guarantee per sector
20-year data retention at 125°C
— Reliable operation for the life of the system
89-ball FBGA package
data input voltages as determined by the voltage on
the V
signals
executing erase/program functions in other bank
wrap-around
sequence
32 Kword sectors
and fifteen 32 Kword sectors; Banks B and C each
contain forty-eight 32 Kword sectors
address range and eight at the bottom of the address
range
TM
(Secured Silicon) Sector region
IO
ADVANCE INFORMATION
pin
IO
) Feature
Refer to AMD’s Website (www.amd.com) for the latest information.
PERFORMANCE CHARCTERISTICS
HARDWARE FEATURES
Read access times at 66/54 MHz (C
— Burst access times of 11/13.5 ns at industrial
— Synchronous latency of 56/69 ns
— Asynchronous random access times of 45/50/55 ns
Power dissipation (typical values, C
— Burst Mode Read: 10 mA
— Simultaneous Operation: 25 mA
— Program/Erase: 15 mA
— Standby mode: 0.2 µA
Handshaking feature
— Provides host system with minimum possible latency
— Reduced Wait-state handshaking option further
Hardware reset input (RESET#)
— Hardware method to reset the device for reading array
WP# input
— Write protect (WP#) function allows protection of the
Persistent Sector Protection
— A command sector protection method to lock
— Sectors can be locked and unlocked in-system at V
Password Sector Protection
— A sophisticated sector protection method to lock
ACC input: Acceleration function reduces
programming time; all sectors locked when ACC =
V
IL
temperature range
by monitoring RDY
reduces initial access cycles required for burst
accesses beginning on even addresses
data
four highest and four lowest 4 kWord boot sectors,
regardless of sector protect status
combinations of individual sectors and sector groups
to prevent program or erase operations within that
sector
level
combinations of individual sectors and sector groups
to prevent program or erase operations within that
sector using a user-defined 64-bit password
Publication# 30491
Issue Date: October 23, 2003
L
=30 pF)
Rev: A Amendment:+3
L
= 30 pF)
CC