am42bds6408h Meet Spansion Inc., am42bds6408h Datasheet - Page 37

• Manufacturer Part Number: am42bds6408h
• Description: Cmos 1.8 Volt-only Simultaneous Read/write, Burst Mode Flash Memory, And 8 Mbit 512 K X 16-bit Sram
• Manufacturer: Meet Spansion Inc.

The device offers accelerated program operations
through the ACC input. When the system asserts V
on this input, the device automatically enters the
Unlock Bypass mode. The system may then write the
t wo - c y c le U n l o ck B y p a s s p ro gra m c o m m a n d
sequence. The device uses the higher voltage on the
ACC input to accelerate the operation.
Figure 4, “Program Operation,” on page 35
the algorithm for the program operation. Refer to the
Erase/Program Operations table in the AC Character-
istics section for parameters, and
chronous Program Operation Timings: AVD# Latched
Addresses,” on page 66
Program Operation Timings: WE# Latched Addresses,”
on page 68
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
October 23, 2003
Note: See Table 16 for program command sequence.
Increment Address
Figure 4. Program Operation
for timing diagrams.
in progress
Embedded
algorithm
Program
and
No
Command Sequence
Figure 33, “Synchronous
Write Program
Last Address?
Programming
from System
Verify Data?
A D V A N C E
Completed
Data Poll
START
Figure 31, “Asyn-
Yes
Yes
illustrates
No
Am42BDS6408H
HH
I N F O R M A T I O N
trols or timings during these operations.
“Command Definitions,” on page 40
and data requirements for the chip erase command
sequence.
When the Embedded Erase algorithm is complete, that
bank returns to the read mode and addresses are no
longer latched. The system can determine the status of
the erase operation by using DQ7 or DQ6/DQ2. Refer
to the
information on these status bits.
Any commands written during the chip erase operation
are ignored. However, note that a hardware reset
immediately terminates the erase operation. If that
occurs, the chip erase command sequence should be
reinitiated once that bank has returned to reading array
data, to ensure data integrity.
The host system may also initiate the chip erase
command sequence while the device is in the unlock
bypass mode. The command sequence is two cycles
cycles in length instead of six cycles. See
“Command Definitions,” on page 40
unlock bypass command sequences.
Figure 5, “Erase Operation,” on page 37
algorithm for the erase operation. Refer to the
Erase/Program Operations table in the AC Character-
istics section for parameters and timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two
additional unlock cycles are written, and are then fol-
lowed by the address of the sector to be erased, and
the sector erase command.
nitions,” on page 40
requirements for the sector erase command sequence.
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm auto-
matically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or
timings during these operations.
After the command sequence is written, a sector erase
time-out of no less than 50 µs occurs. During the
time-out period, additional sector addresses and sector
erase commands may be written. Loading the sector
erase buffer may be done in any sequence, and the
number of sectors may be from one sector to all sec-
tors. The time between these additional cycles must be
less than 50 µs, otherwise erasure may begin. Any
sector erase address and command following the
exceeded time-out may or may not be accepted. It is
recommended that processor interrupts be disabled
during this time to ensure all commands are accepted.
“Write Operation Status” section on page 43
shows the address and data
Table 16, “Command Defi-
shows the address
for details on the
illustrates the
Table 16,
Table 16,
35
for