lc890561w Sanyo Semiconductor Corporation, lc890561w Datasheet - Page 11

• Manufacturer Part Number: lc890561w
• Description: Cmos Digital Audio Interface Receiver With Built-in Data Buffer Memory
• Manufacturer: Sanyo Semiconductor Corporation

9. Built-in Regulator (VREF)
• It has built-in regulator that can step down 3.3V to 1.8V in order to supply voltage into logic part.
• VREF is pin for voltage smoothing which can output regulator and connects the capacity as shown below.
10. Analog Source Mode
• The analog source mode is entered under the following conditions.
• In the analog source mode, the oscillation amplifier clock or the externally supplied clock are used.
• Each signal in the analog source mode is described below.
−VCO holds the status of free-run oscillation when SMOD is set and also when no signal is input.
−ERROR pin outputs high and DATAO pin outputs SDIN input data.
−XSTATE pin outputs high after about 512*LRCK(fs) (LRCK=48kHz or 96kHz) counts after XSTATE pin outputs low.
−The clock set with XADC command is output from XMCK.
−The output of BCK and LRCK are as follows.
−When the analog source mode is selected with the SMOD command.
−When the input pin selected for data demodulation is no signal.
C0
VREF
C1
12MHz to 25MHz
Table 10.1 BCK and LRCK Outputs with Analog Source
12.288MHz
24.576MHz
XIN pin
Figure 9.1 Composition of the regulator output
LC890561W
10µF
C0
3.072MHz
6.144MHz
BCK pin
XIN/4
0.1µF
C1
LRCK pin
XIN/256
48kHz
96kHz
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