lc890561w Sanyo Semiconductor Corporation, lc890561w Datasheet - Page 12

• Manufacturer Part Number: lc890561w
• Description: Cmos Digital Audio Interface Receiver With Built-in Data Buffer Memory
• Manufacturer: Sanyo Semiconductor Corporation

11. Setting of MODE0 and MODE1
• Selected operation mode with MODE0 and MODE1 terminals.
• In the normal mode, when fs of input data is out of the reception setting range or the fs calculation range (≠target fs
• In the input fs free mode, the reception range is set up without any restriction and fs calculation result is set so that it
frequency ± 3 to 4%), ERROR is output high even if PLL is locked.
is not reflected in ERROR output. ERROR output will be set to low if PLL is locked.
(a) Mode1: Normal mode
(b) Mode2: Input fs free mode A (Terminal setting priority)
(c) Mode3: Test mode
(d) Mode4: Input fs free mode B (Terminal setting priority)
−Do not set this mode for the test.
−Input data fs of 32kHz to 192kHz is received only when CKOUT=256fs.
−The proper reception of data over 96kHz will not be ensured when other than 256fs is used for CKOUT output
−Restriction of input fs is canceled.
−12.288MHz or 24.576MHz clock is supplied to XIN.
−The receiving range of input data is based on a setup of CKOUT output.
−Fs calculation of input data is performed in the possible range. (fs ± 3 to 4%)
−Restriction of input fs is canceled.
−12MHz to 25MHz arbitrary clock is supplied to XIN.
−The reception range of input data is based on a setup of the CKOUT output.
−Input fs is not calculated. In this case, all F0, F1 and F2 output low.
−Output data delay after recovery processing cannot be set. However, the delay setting of the SDIN input data is
possible.
setting.
Mode No.
1
2
3
4
MODE1 pin
0
0
1
1
Table 11.1 Setting operating mode
LC890561W
MODE0 pin
0
1
0
1
Normal mode
Fs free mode A
Test mode
Fs free mode B
Function
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