lc890561w Sanyo Semiconductor Corporation, lc890561w Datasheet - Page 21

• Manufacturer Part Number: lc890561w
• Description: Cmos Digital Audio Interface Receiver With Built-in Data Buffer Memory
• Manufacturer: Sanyo Semiconductor Corporation

12.7.2 Upon Error Recovery (Lock)
• When preamble B, M and W are detected, PLL is locked and data demodulation begins.
• DATAO and DATAO2 output data are output from the L/R clock edge after ERROR goes low.
• The start timing of the ERROR flag, and the DATAO and DATAO2 output data are shown in Figure 12.8.
• The above operation is in case the delay setup is not done. For information on operations with delay settings, see
12.8 Channel Status Emphasis Information Output (EMPHA)
• EMPHA outputs channel status information that indicates the presence or absence of 50/15µsec pre-emphasis.
• EMPHA is output immediately after the detection of ERROR even during high output.
12.9 Channel Status Bit 1 Output (AUDIO)
• AUDIO outputs bit 1 of the channel status that indicates whether transfer data has PCM audio data or data other than
• AUDIO is output immediately after the detection of ERROR even during high output.
section “13. Output Data Delay Function”.
audio.
Internal lock signal
ERROR
DATAO
LRCK
Figure 12.8 Data Processing at Data Demodulation Start (non delay setting)
EMPHA pin
AUDIO pin
H
H
L
L
Table 12.7 EMPHA Output
Output start from LRCK edge immediately after ERROR flag is lowered
Table 12.8 AUDIO Output
LC890561W
OK
Data other than audio (CS bit 1 = H)
3ms to 300ms
PCM audio data (CS bit 1 = L)
50/15 µ s pre-emphasis
No pre-emphasis
Output condition
Output condition
Data
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