lc890561w Sanyo Semiconductor Corporation, lc890561w Datasheet - Page 22

• Manufacturer Part Number: lc890561w
• Description: Cmos Digital Audio Interface Receiver With Built-in Data Buffer Memory
• Manufacturer: Sanyo Semiconductor Corporation

12.10 First 48 Channel Status Bits Update Flag Output (CSFLAG)
• CSFLAG compares the first 48 bits of channel status data of the previous block with those of the current block and
• CSFLAG outputs high regardless of the comparison result until ERROR outputs low. After ERROR output becomes
12.11 Non-PCM Burst Preamble Detection Signal Output (BPSYNC)
• BPSYNC outputs low while Non-PCM burst preamble Pa, Pb, Pc and Pd output, when Pa and Pb are detected
• Pa, Pb, Pc and Pd are detected from the receive data even when an input parity error occurs.
outputs low in case they are the same, and high in case they are different, for 1 block of 192 frames. Therefore the
channel status data output after the falling edge of the CSFLAG is the latest data.
low, CSFLAG outputs low after the first 48bit data of the previous data and the current data have been confirmed to
be identical.
following continuous all zero data of two frame. However, when output data delay is set up, low period of a BPSYNC
signal and the output period of the Non-PCM burst preamble Pa, Pb, Pc, and Pd do not match. In this case, BPSYNC
is output ahead of Pa, Pb, Pc, and Pd data.
Input data
CSFLAG
LRCK
Input data
BPSYNC
DATAO
LRCK
bit 191
M191
Figure 12.10 Timing Chart for Pa, Pb, Pc and Pd Detection Signal Output
CSFLAG pin
Figure 12.9 Timing Chart for Channel Status Update Flag Output
W191
bit 191
H
L
000h 000h
bit 0
B
000h 000h
bit 0
W
Table 12.9 CSFLAG Output
LC890561W
000h
Pa
Preamble
000h 000h 000h
Pb
bit 46
W46
Previous data current data are identical
Pc
Previous data differs from current data
bit 47
M47
Become “H” when not identical to previous block
Pd
Output condition
bit 47
W47
2
Pa
2
Pb
bit 48
M48
Burst payload
3
Pc
bit 48
W48
3
Pd
4
bit 49
M49
2
4
2
bit 49
W49
bit 50
M50
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