lc890561w Sanyo Semiconductor Corporation, lc890561w Datasheet - Page 37

• Manufacturer Part Number: lc890561w
• Description: Cmos Digital Audio Interface Receiver With Built-in Data Buffer Memory
• Manufacturer: Sanyo Semiconductor Corporation

IMOD
FSEL
VSEL
CKPO
XSTP
XCKS
EWT1
XCKS
DI15
DI7
EWT0
XSTP
DI14
DI6
CL pin setting
F0/FSB0, F1/FSB1, F2/DLMP pin setting
VF/DATAO2 pin setting
CKOUT output polarity setting
XSTATE output polarity setting
XMCK output setting while PLL is locked (Enable, when XCNT= 1)
0
1
0
1
0
1
0
1
0
1
0
1
DI13
:
:
:
:
:
:
:
:
:
:
:
:
DI5
0
0
Data readout is performed with normal L clock (default)
Data readout is performed with normal H clock
F0, F1, F2; Input sampling frequency calculated signal output
(default)
FSB0, FSB1, DLMP; The monitor signal output for a delay setting
VF; Validity flag output (default)
DATAO2; Data output after demodulation
Normal output (default)
Inverted-phase output
Normal H output (default)
Normal L output
Output according to the operation of oscillation amplifier (default)
Stop output only when PLL is locked during the continuous
operation of oscillation amplifier
CCB address: 0xEB
LC890561W
CKPO
DI12
DI4
0
DOM1
VSEL
DI11
DI3
DOM0
FSEL
DI10
DI2
DI1
DI9
0
0
DLPO
IMOD
DI0
DI8
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