lc890561w Sanyo Semiconductor Corporation, lc890561w Datasheet - Page 16

• Manufacturer Part Number: lc890561w
• Description: Cmos Digital Audio Interface Receiver With Built-in Data Buffer Memory
• Manufacturer: Sanyo Semiconductor Corporation

12.5 Serial Audio Data Input and Output
12.5.1 Output Data Format (DATAO, DATAO2, DOSEL0, DOSEL1)
• DATAO and DATO2 output the digital data after demodulation. DATAO2 should be switched by the VSEL
• The output data format is set with DOSEL0 and DOSEL1 terminals, or the DOSW command. The output data is 24bit
• Data is output in synchronization with the falling edge of BCK from the edge of LRCK immediately after the ERROR
command since DATAO2 is sharing pin with validity flag output.
I
flag goes low. However, this is the case that the delay setup is disabled (initial setting). When the delay setup is
effective, DATAO is output after the delay time set. The delay setting is not applicable to DATA02. For information
about these settings, see section “13. Output Data Delay Function”.
2
S output when setup is DOSW=1. The setup of DOSW is given priority over DOSEL0 and DOSEL1.
LRCK (O)
BCK (O)
DATAO (O)
DATAO2 (O)
LRCK (O)
BCK (O)
DATAO (O)
DATAO2 (O)
LRCK (O)
BCK (O)
DATAO (O)
DATAO2 (O)
DOSEL1 pin
0
0
1
1
LSB
MSB
Table 12.5 Data output format Selection (DOSW = 0)
MSB
Max. 24bit
Figure 12.2 Data Output Timing Charts
(1) (2) (3): Setting with DOSEL0, DOSEL1
MSB
DOSEL0 pin
(4): Setting with the DOSW command
(0): Setting with DOSEL0, DOSEL1
24bit
L-ch
L-ch
L-ch
0
1
0
1
16, 20, 24bit
LSB
LC890561W
LSB
(0) 24bit MSB-first left justified
(1) 24bit MSB-first right justified
(2) 20bit MSB-first right justified
(3) 16bit MSB-first right justified
LSB
MSB
DATAO and DATAO2 pin
MSB
Max. 24bit
MSB
24bit
R-ch
R-ch
R-ch
16, 20, 24bit
LSB
LSB
LSB
MSB
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