lc890561w Sanyo Semiconductor Corporation, lc890561w Datasheet - Page 30

• Manufacturer Part Number: lc890561w
• Description: Cmos Digital Audio Interface Receiver With Built-in Data Buffer Memory
• Manufacturer: Sanyo Semiconductor Corporation

13.3 Time Lag of the Command Setup (DTMA[4:0], DTMB[3:0], DTMC[2:0], DTMX[4:0], DTMY[3:0])
• DTMA [4:0], DTMB [3:0], DTMC [2:0], DTMX [4:0] and DTMY [3:0] commands are performed synchronizing with
• Moreover, the minimum interval of a command setup becomes 1 LRCK period.
• Furthermore, data processing by command setup is performed after 1 LRCK period progress.
• Setup, change and cancel of the delay time are processed per command.
• Setup, change and cancel of the command in the same address are performed for the data of the target input sampling
• Cancel of the command is the case where the delay time is set as 0.
the rising edge (the falling edge is used for the I
LRCK cycle at the maximum arises after setting up the command until it is executed.
frequency.
Commands
Commands
Set-up of
State of
DATAO
LRCK
CE
CL
DI
B0
B1
Figure 13.9 Timing Chart from a Command Setup to Execution
A2
A3
ex.) Delay = 90ms
DI0
Delay = 90ms
DI1 DI2
Time lag of command setting
2
LC890561W
S data format setup) of LRCK clock. Therefore, the time lag of 1
Before (90ms)
DI12 DI13 DI14 DI15
Change point
Time lag of data output
ex.) Delay = 40ms
Delay = 40ms
Microcontroller
After (40ms)
interface
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