lc890561w Sanyo Semiconductor Corporation, lc890561w Datasheet - Page 18

• Manufacturer Part Number: lc890561w
• Description: Cmos Digital Audio Interface Receiver With Built-in Data Buffer Memory
• Manufacturer: Sanyo Semiconductor Corporation

12.5.3 Output Data Changing (DATAO, DATAO2, SDIN)
• DATAO and DATAO2 output demodulation data when PLL is locked, and output SDIN input data when PLL is
• During the selection of SDIN input data, it must be switched to the clock source that is in synchronized with SDIN data.
• SDIIN input data is output to DATAO and DATAO2 with the SMOD command setting regardless of the lock /
• DATAO and DATAO2 output can be muted forcibly with setting of the DOM[1:0] commands.
12.5.4 Data System Diagram (DIN0, DIN1, DIN2, SDIN, DOUT, DATAO, DATAO2)
• Data system diagram is shown below.
• The delay setup for DATAO is possible. However, the delay setup for DATAO2 is impossible because DATAO2
• DIN0 to DIN2 and SDIN input data are output to DATAO and DATAO2 behind two frames. Delay setup of output
• Since DATAO2 shares the pin with the validity flag output, it should be changed by the VSEL command. The initial
unlocked. This switching is automatically performed according to the state of PLL lock or unlock.
unlock state of PLL. In the case of switching PLL in the lock state, clock source is also switched to XIN. Furthermore,
an ERROR flag also outputs high and a XSTATE signal also changes.
does not go through a memory.
data is processed with the DATAO output with 2-frame delay against the input data as delay for 0ms.
value of VSEL is the validity flag output.
(XSTP = 0)
(XSTP = 0)
SDIN
DIN0
DIN1
DIN2
PLL state
PLL state
DATAO2
DATAO2
XSTATE
XSTATE
ERROR
ERROR
DATAO
DATAO
Figure 12.4 DATAO and DATAO2 Outputs Data Chang Timing Charts
(3in/1out)
MUX
SDIN data
UNLOCK
Demodulation data
Figure 12.5 Data System Diagram
Data register
LOCK
VF
DIR
LC890561W
(a): Lock-in stage
(b): Unlock stage
Muted
[SMOD]
Muted
LOCK
[VSEL]
UNLOCK
Buffer
RAM
Demodulation data
SDIN data
DATAO
VF/DATAO2
DOUT
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