lc890561w Sanyo Semiconductor Corporation, lc890561w Datasheet - Page 23

• Manufacturer Part Number: lc890561w
• Description: Cmos Digital Audio Interface Receiver With Built-in Data Buffer Memory
• Manufacturer: Sanyo Semiconductor Corporation

12.12 Input Sampling Frequency Calculation Signal Output (F0, F1, F2)
• By inputting 12.288MHz or 24.576MHz oscillation amplifier clock or external input clock, input sampling
• This processing is completed until preamble B is counted to eight after PLL is locked. Therefore, it is fixed by the
• If the frequency other than 12.288MHz or 24.576MHz is set, the F0, F1 and F2 outputs are not guaranteed.
• This information can also be read with the microcontroller interface.
• The fs of input data except input fs free mode is within the calculation range.
12.13 Validity Flag Output (VF)
• VF/DATAO2 outputs the validity flag.
• VF/DATAO2 shares the pin with the demodulated audio data output pin (delay setup is impossible). Setting as
frequencies of 32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz and 192kHz are calculated and the result is
output from F0, F1 and F2.
time the ERROR flag is lowered, and it will not change until PLL is unlocked.
VSEL=0 (default) makes output validity flag possible.
Note: *Output when PLL is unlocked or when a sampling frequency cannot be calculated.
Table 12.10 Fs Calculation Results when 12.288MHz or 24.576MHz is Set (Ta = 25°C, V DD = 3.3V)
F2 pin
H
H
H
H
L
L
L
L
F1 pin
H
H
H
H
L
L
L
L
VF pin
H
L
F0 pin
H
H
H
H
L
L
L
L
Table 12.11 VF Output
LC890561W
Target fs frequency
Out of Range
176.4kHz
44.1kHz
88.2kHz
192kHz
32kHz
48kHz
96kHz
Error (possibility of burst data)
No (no burst data)
Output condition
170.7kHz to 180.7kHz
186.2kHz to 198.1kHz
30.8kHz to 33.3kHz
42.4kHz to 45.8kHz
46.2kHz to 49.9kHz
85.4kHz to 91.7kHz
93.1kHz to 99.0kHz
Calculation range
-
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