w65c265s Western Design Center, Inc., w65c265s Datasheet - Page 13

• Manufacturer Part Number: w65c265s
• Description: W65c265s 16?bit Microcontroller
• Manufacturer: Western Design Center, Inc.

1.9
The W65C265S Microcomputer provides four full duplex Universal Asynchronous Receiver/Transmitters
(UART) with programmable bit rates. The serial I/O functions are controlled by the Asynchronous
Communication Control and Status Registers (ACSRx). The ACSRx bit assignment is shown in Figure
1-10. The serial bit rate is determined by Timer 3 or 4 for all modes for the UART's. The maximum data
rate using the internal clock is 0.5MHz bits per second (FCLK = 8MHz). The Asynchronous Transmitter
and Asynchronous Receiver can be independently enabled or disabled.
All transmitter and receiver bit rates will occur at one sixteenth of Timer 3 or 4 as selected.
Whenever Timer 3 or 4 is required as a timing source, it must be loaded with the hexadecimal code that
selects the data rate for the serial I/O Port. Refer to Table 1-3 for a table of hexadecimal values that
represent the desired data rate.
WDC Standard UART Features
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1.9.1 Asynchronous Transmitter Operation
The transmitter operation is controlled by the Asynchronous Control and Status Register (ACSRx. The
transmitter automatically adds a start bit, parity bit and one or two stop bits as defined by the ACSRx. A
word of transmitted data is 7 or 8 bits of data.
The Transmitter Data Register (ARTDx) is located at addresses $DF71, $DF73, $DF75, and $DF77 and
is loaded on a write. The Receiver is read at this same address.
The Transmitter Interrupt is controlled by the Asynchronous Control Status Register bit ACSRx1.
IRQAT = ACSRx0((ACSRx1B)(DATA REGISTER EMPTY) + (ACSRx1)(DATA REGISTER AND SHIFT
REGISTER EMPTY))
Serial
Data
7 or 8 bit data with or without Odd or Even parity.
The Transmitter has 1 stop bit with parity or 2 stop bits without parity.
The Receiver requires only 1 stop bit for all modes.
Both the Receiver and Transmitter have priority encoded interrupts for service routines.
The Receiver has error detection for parity error, framing error, or over-run error conditions that may
require re-transmission of the message.
The Receiver Interrupt occurs due to a receiver data register full condition.
The Transmitter Interrupt can be selected to occur on either the data register empty (end-of-byte
transmission) or both the data register empty and the shift register empty (end-of-message
transmission) condition.
Universal Asynchronous Receiver/Transmitters (UARTs)
Start
Bit
Figure 1-8 Asynchronous Transmitter Mode with Parity
0
1
2
3
4
5
6
7
Parity
Bit
Stop
Bit
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