w65c265s Western Design Center, Inc., w65c265s Datasheet - Page 3

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w65c265s

Manufacturer Part Number
w65c265s
Description
W65c265s 16?bit Microcontroller
Manufacturer
Western Design Center, Inc.
Datasheet
The WDC W65C265S microcomputer is a complete fully static 16-bit computer fabricated on a single chip
using a Hi-Rel low power CMOS process. The W65C265S complements an established and growing line of
W65C products and has a wide range of microcomputer applications. The W65C265S has been developed
for Hi-Rel applications and where minimum power is required.
The W65C265S consists of a W65C816S (Static) Central Processing Unit (CPU), 8K bytes of Read Only
Memory (ROM), 576 bytes of Random Access Memory (RAM), Processor defined cache under software
control, eight 16-bit timers with maskable interrupts, high performance interrupt-driven Parallel Interface Bus
(PIB), four Universal Asynchronous Receivers and Transmitters (UART) with baud rate timers, Monitor
"Watch Dog" Timer with "restart" interrupt, twenty-nine priority encoded interrupts, Built-in Emulation features,
Time of Day (ToD) clock features, Twin Tone Generators (TGx), Bus Control Register (BCR) for external
memory bus control, interface circuitry for peripheral devices, ABORT input for low cost virtual memory
interface, and many low power features.
The innovative architecture and demonstrated high performance of the W65C265S CPU, as well as
instruction simplicity, result in system cost-effectiveness and a wide range of computational power. These
features make the W65C265S a leading candidate for 16-bit microcomputer applications especially where
task oriented processing is desired.
This product description assumes that the reader is familiar with the W65C816S CPU hardware and
programming capabilities. Refer to the W65C816S Data Sheet for additional information.
Hi-Rel low power CMOS process
Operating TA =0ºC to +70ºC
Single 2.8V to 5.5V power supply
Static to 8MHz clock operation
W65C816S compatible CPU
Single chip microcomputer
16Mbyte linear address space
8- and 16-bit parallel processing
Variable length stack
True indexing capability
Twenty-four address modes
Decimal or binary arithmetic
Pipeline architecture
Fully static CPU
2 Tone Generators
64 CMOS compatible I/O lines
8K x 8 ROM on-chip
576 x 8 RAM on-chip
WAIt for interrupt
SToP the clock
Fast oscillator start and stop feature
KEY FEATURES OF THE W65C265S
INTRODUCTION
Twenty-nine priority encoded interrupts
Four UARTS's
Time of Day (ToD) clock features
8 x 16 bit timer/counters
Bus Control Register
Many bus operating features and modes
8 Programmable chip select outputs
Low cost surface mount 84 and 100 lead packages
Macro and Cross assemblers available
C compilers available
BRK software interrupt
RESET "RESTART" interrupt
NMIB Non-Maskable interrupt
ABORT interrupt
COP software interrupt
IRQB level interrupt
8 timer edge interrupts
6 edge interrupts
PIB interrupt
4 UART Receiver interrupts
4 UART Transmitter interrupts
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