w65c265s Western Design Center, Inc., w65c265s Datasheet - Page 34

• Manufacturer Part Number: w65c265s
• Description: W65c265s 16?bit Microcontroller
• Manufacturer: Western Design Center, Inc.

2.1
The WEB signal is high when the microprocessor is reading data from external memory or I/O and high
when it is reading or writing to internal memory or I/O. When WEB is low the microprocessor is writing to
external memory or external I/O. The WEB signal is bi-directional; when BE is low this is an input for DMA
operations to on-chip RAM or I/O. When BE is high the internal microprocessor controls WEB.
2.2
2.2.1 The RUN function of the RUN output is pulled low as the result of a WAI or STP instruction. RUN is
2.2.2 When BCR3=1 (emulation mode), the SYNC function (SYNC=1 indicates an opcode fetch) is
2.2.3 The BE input has no effect on RUN.
2.2.4 When RUN goes low the PHI2 signal may be stopped when high or low; however, it is recommended
2.2.5 The WAI instruction pulls RUN low during PHI2 high time. RUN stays low until an enabled interrupt is
2.2.6 The STP instruction pulls RUN low during PHI2 high time and stops the internal PHI2
2.2.7 FCLK can be started or stopped by writing to System Speed Control Register (SSCR) bit 0. When
2.3
PHI2 output is the main system clock used by the microprocessor for instruction timing, general on-chip
memory, and I/O timing. The PHI2 clock source is either CLK or FCLK depending on the value of System
Speed Control Register bit 1 (SSCR1). When SSCR1=0, then CLK is the PHI2 clock source. When
SSCR1=1, then FCLK is the PHI2 clock source.
2.4
CLK and FCLK inputs are used by the timers, for PHI2 system clock generation, counting events or
implementing Real Time clock type functions. CLK should always be equal to or less than one-fourth the
FCLK clock rate when FCLK is running (see the timer description for more information). CLKOB, FCLKOB
outputs are the inverted CLK and FCLK inputs that are used for oscillator circuits that employ crystals or a
resistor-capacitor time base.
Write Enable (active low) (WEB)
RUN and SYNC outputs with WAI and STP defined (RUN)
used to signal an external oscillator to start PHI2. The processor is stopped when RUN is low.
multiplexed on RUN during PHI2 low time and RUN is multiplexed during PHI2 high time. When
BCR3=0 (normal operating mode), the RUN function is output during the entire clock cycle. An ICE
system can demultiplex RUN to provide full emulation capability for the RUN function.
PHI2 stop in the high state. When RUN goes high due to an enabled interrupt or
internal PHI2 clock is requested to start. The clock control function is referred to as the RUN function
of RUN.
requested or until RESB goes from low to high, starting the microprocessor.
RUN remains low and the clock remains stopped until RESB goes from low to high.
SSCR0=0 (reset forces SSCR0=0), FCLK is stopped. When SSCR0=1, FCLK is started. When
starting FCLK oscillator, the system software should wait (100 milliseconds or an appropriate amount
of time) for the oscillator to be stable before using FCLK.
Phase 2 Clock Output (PHI2)
Clock Inputs (CLKOB, FCLKOB Outputs) (CLK. FCLK)
reset, the
clock.
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