w65c265s Western Design Center, Inc., w65c265s Datasheet - Page 15

• Manufacturer Part Number: w65c265s
• Description: W65c265s 16?bit Microcontroller
• Manufacturer: Western Design Center, Inc.

ACSRx2: Seven- or Eight-Bit Data Select. When ACSRx2=0, the Transmitter and Receiver send and
ACSRx3:
ACSRx4:
ACSRx5:
ACSRx6:
ACSRx7:
Parity Enable. When ACSRx3=0, parity is disabled. Reset clears ACSRx3. When
Odd or Even Parity. When ACSRx4=0 and parity is enabled, then Odd parity is generated
Receiver Enable. The Asynchronous Receiver is enabled when ACSRx5=1. Reset clears
Software Semiphore. ACSRx6 may be used for communications among routines which
Receiver Error Flag. The Receiver logic detects three possible error conditions and sets
receive 7-bit data. The Transmitter sends a total of 10 bits of information (one
start, 7 data, one parity and one stop or 2 stop bits). The Receiver receives 9 or
10 bits of information (one start, 7 data, and one stop or one stop and one parity
bits). When writing to the Transmitter in seven bit mode, bit 7 is discarded.
When reading from the receive data register during seven bit mode, bit 7 is
always zero. When ACSRx2=1, the Transmitter and Receiver send and receive
8-bit data. The Transmitter sends 11 bits of information (one start, 8 data, one
parity and one stop or two stop bits). The Receiver receives 10 or 11 bits of
information (one start, 8 data, one stop or one parity and one stop bit). Reset
clears ACSRx2.
ACSRx3=1, parity is enabled for both the Transmitter and Receiver.
where the number of ones is the data register plus parity bit equal an odd
number of "1's". When ACSRx4=1 and parity is enabled, then Even parity is
generated where the number of ones in the data register plus parity bit equal an
even number of "1's". ACSRx4 is cleared by Reset.
ACSRx5. When ACSRx5=1 the Receiver is enabled and Receiver Interrupts
occur anytime the contents of the Receiver shift register contents are
transferred to the Receiver Data Register. The Receiver Interrupt is cleared
when the Receive Data Register is read. The Receive Data, RXDx, is enabled
on Port 6 when ACSRx5=1. When ACSRx5=0, all Receiver operation is
disabled and all Receive logic is cleared, the Receiver data register bits 0-6 are
not affected and bit 7 is cleared.
access the UARTx. This bit has no effect on the UART operation and is cleared
upon Reset. The bit can be thought of as a manually set busy signal.
ACSRx7: parity, framing or over-run. A parity error occurs when the parity bit
received does not match the parity generated on the receive data. A framing
error occurs when the stop bit time finds a "0" instead of a "1". An over-run
occurs when the last data in the Receiver Data Register has not been read and
new data is transferred from the Receive Shift Register. ACSRx7 is cleared by
Reset or upon writing a "1" to ACSRx7. Writing a "0" to ACSR7 has not effect on
ACSRx7.
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