w65c265s Western Design Center, Inc., w65c265s Datasheet - Page 9

• Manufacturer Part Number: w65c265s
• Description: W65c265s 16?bit Microcontroller
• Manufacturer: Western Design Center, Inc.

1.6
1.6.1 A bit of these registers is set to a "1" in response to an interrupt signal from a source. Sources
1.6.1.1
1.6.1.2
1.6.1.3
1.7
TIER, EIER, and UIER are the interrupt enable registers. Reading an IER register reads its contents and
puts the value on the internal data bus. Writing an IER writes a value from the data bus into the register.
Setting a bit in an IER to "1" permits the interrupt corresponding to the same bit in the IFR to cause a
processor interrupt. If a WAI instruction has been executed prior to the interrupt occurring and the part is in
the non-emulation mode (BCR3=0). The RUN pin will be low until the interrupt occurs and will then go high
to indicate the part is running.
Note that the "I" flag in the microprocessor status register must be cleared with an instruction before any of
the interrupts controlled by TIER, EIER, and UIER can occur.
Interrupt Flag Registers (TIFR,EIFR,UIFR)
Interrupt Enable Registers (TIER,EIER,UIER)
specified as level-triggered assert the corresponding IFR bit if an edge occurs and is held to a
"1" as long as the IRQB input is held low. Sources specified as edge-triggered assert the
corresponding IFR bit upon and only upon transition to the specified polarity. Note that
changes for edge-triggered bits are asynchronous with PHI2.
Read of a IFR register. A read from an IFR register transfers its value to the internal data
Write to an IFR register. A write of a "1" to any bits of these registers disasserts those bits
Interrupt Priority. If more than one bit of the Interupt Flag Registers are set to a "1" and
bus.
but has no further effect when execution of that write instruction is completed;
that is, the bit is reset by a pulse but not held reset. A write of a "0" to any bits of
these registers has no effect. (Note that you must write a "1" to the
corresponding IFR bit after the interrupt has been serviced; otherwise, the
interrupt will continue to occur.)
enabled, the vector corresponding to the highest memory map location and bit
number asserted is used. For example, if both the TIFR1 and EIFR3 were
asserted and enabled, then the vector corresponding to EIFR3 would be used.
For another example, if both the TIFR3 and EIFR0 were asserted and enabled,
then the vector corresponding to EIFR0 would be used.
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