w65c265s Western Design Center, Inc., w65c265s Datasheet - Page 7

• Manufacturer Part Number: w65c265s
• Description: W65c265s 16?bit Microcontroller
• Manufacturer: Western Design Center, Inc.

1.5
1.5.1 Upon Timer clock input negative edge the timer counter is decremented by 1.
1.5.2 A write to the timer low counter writes the timer low latch.
1.5.3 A read of the timer high or low counter reads the timer high or low counter.
1.5.4 Upon Timer clock input negative edge when the timer low counter reaches zero, the timer high
1.5.4.1
1.5.4.2
1.5.5 A write to the Timer high counter writes to the timer high latch and this sequence occurs:
1.5.5.1
1.5.5.2
1.5.6 Timer 0 is disabled after RESB and is activated by the first TER0 transistion from "0" to "1" (the first
1.5.6.1
1.5.7 A timer must be reloaded after it is disabled with TERx for it could have been stopped with all $FFFF's
The Timers
counter is decremented by 1. Upon Timer clock input positive edge, when the timer high
counter reaches zero, this sequence occurs:
The Timer sets its associated interrupt flag. If the interrupt is enabled the MPU is then
The Timer high counter is loaded from the timer high latch, and timer low counter is loaded
The timer high latch is loaded from data bus.
The timer low counter is loaded from the timer low latch, and the timer high counter is loaded
load of Timer 0).
The Timer 0 counter is reloaded with the value in the Timer 0 latches when the TER0 bit 0
and when restarted will require full length count down.
Number
T7
T6
T5
T4
T3
T2
T1
T0
interrupted and control is transferred to the vector associated with the interrupt.
When Timer 0 times out, the W65C265S is restarted: on-chip logic pulls RESB
pin low for 2 CLK cycles and releases RESB to go high, "restarting" the
W65C265S.
from timer low latch.
from the timer high latch.
makes a transition from a "0" to "1". TER0 transition from a "1" to a "0" has no
effect on the timer.
UART Baud Rate or Pulse,
Pulse Width Measurement
Table 1-2 The Timer Functions
Prescaled Interrupt
Monitor Watch Dog
UART Baud Rate
Tone Generator
Tone Generator
Timer Function
Input/Output
Time of Day
FCLK/16
TCR0=0
FCLK
FCLK
FCLK
FCLK
FCLK
CLK
CLK
TCR0=1
P60
-
-
-
-
-
-
-
7