w65c265s Western Design Center, Inc., w65c265s Datasheet - Page 36

• Manufacturer Part Number: w65c265s
• Description: W65c265s 16?bit Microcontroller
• Manufacturer: Western Design Center, Inc.

2.6
2.6.1 When RESB is low for 2 or more processor PHI2 cycles all activity on the chip stops and the chip
2.6.2 After a Reset, all I/O pins become inputs. Because of NOR gates on the inputs, RESB disables all
2.6.3 When RESB goes from low to high, RUN goes high, the Bus Control Register is initialized to $89 if BE
2.6.4 The reset sequence takes 9 cycles to complete before loading the first instruction opcode.
2.6.5 RESB is a bidirectional pin which is pulled low internally for "restarting" due to a "monitor time out",
2.7
VDD is the positive power supply and has a range of 2.8V to 5.5V for use in a wide range of
2.8
VSS is the system logic ground. All voltages are referenced to this supply pin.
2.9
2.9.1 All ports, except Port 7, which is an output Port, are bi directional I/O ports. Each of these bi-
2.9.2 Port 7 has a Chip Select register (PCS) that is used to enable Chip Selects (CSxB). A "1" in bit x of
2.10 Address Bus (Axx)
Ports 0, 1, and 3 are also the address bus A0-A23 when configured by the Bus Control Register (BCR).
When BCR0 and BCR7 are set to "1" and BCR3=0 (normal operating mode) for external memory
addressing, Axx are all "1's" when addressing on-chip memory. When BCR3=1 (emulation mode), the
address bus is always active so that an emulator can trace internal read and write operations.
2.11 Data Bus (Dx)
Port 2 is the data bus D0-D7 when configured by the Bus Control Register (BCR). (See section 1.4 for BCR
mode selection.) When BCR0 and BCR7 are set to a "1" and BCR3=0 (normal operating mode) for external
memory addressing, Dx are all "1's" when addressing on-chip memory. When BCR3=1 (emulation mode),
the data bus is always active so that an emulator can trace internal read and write operations. During
external memory cycles the data bus is in the Hi-Z state during PHI2 low time.
Reset Input/Output (active low) (RESB)
goes into the static low power state.
input buffers. The inputs will not float due to the bus holding devices while RESB is low. Inputs that
are unaffected by RESB are BE and WEB.
is low or to $00 if BE is high. The MPU then begins the power-up reset interrupt sequence in which
the program counter is loaded with the reset vector that points to the first instruction to be executed.
(See WDC's W65C816S microprocessor data sheet for more information and instruction timing.)
Timer M times out causing a system Reset. (See section 1.5, The Timers for more information.)
Positive Power Supply (VDD)
applications.
Internal Logic Ground (VSS)
I/O Port Pins (Pxx)
directional Ports has a port data register (PDx) and port data direction register (PDDx). A zero ("0") in
PDDxx defines the associated I/O pin as an input with the output transistors in the "off" high
impedance state. A one ("1") in PDDxx defines the I/O pin as an output. A read of PDx always
"reads" the pin. After reset, all Port pins become input pins with both the data and data direction
registers reset to 0.
PCSx enables Chip Select CSx- to be output over P7x while a "0" in PCSx specifies the value in the
output data register is to be output on P7x. Port 7 data register is set to all "1's" after Reset, and PCS
is cleared to all "0's" after Reset.
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