w65c265s Western Design Center, Inc., w65c265s Datasheet - Page 38

• Manufacturer Part Number: w65c265s
• Description: W65c265s 16?bit Microcontroller
• Manufacturer: Western Design Center, Inc.

2.18 Timer 4 Input and Output (TIN, TOUT)
Timer 4 is controlled by TCRx and TERx. When the UART is not in use, Timer 4 can be used for counting
input negative pulses on TIN. Timer 4 can also be used to put out a square wave or rectangular wave form
on TOUT. When counting negative pulses on TIN the TIN frequency should always be less than one-half
the frequency of PHI2. TOUT changes state on every time-out of Timer 4; therefore, varying waveform and
frequency depends on the timer latch values and may be modified under software control. TIN is
multiplexed on P60 and TOUT is multiplexed on P61.
2.19 Bus Available/Disable Output Data (BA)
The BA output indicates the microprocessor is using the internal data and address buses when BA is high.
The microprocessor is using the external bus when BA is low, then an external device can use the bus without
slowing down processing. BE must be used to gain access to the WEB and address bus. When DODB is
low (during PHI2 high) then the microprocessor is writing data to the external data bus. The other devices
using the bus should disable their outputs. This signal could be thought of as a valid memory address
negative edge for sampling the address bus on the negative edge. When BCR3=1(emulation mode) the
DODB function is multiplexed on BA during PHI2 high time and BA is multiplexed during PHI2 low time.
When BCR3=0 (normal mode) the BA is output during PHI2 low time and a 1 level is output during PHI2 high
time.
2.20 Tone Generator Outputs (TGx)
The Twin Tone Generator outputs (TGx) are synthesized 16 step cosine waveform outputs as described in
Section 2.21 Twin Tone Generators.
2.21 Parallel Interface Bus (PIB)
2.22 Pulse Width Measurement Input (PWM)
The Pulse Width Measurement (PWM) input will cause the Timer 7 (T7) counter contents to be transferred
to the T7 output latches on the edge(s) selected by the Timer Control Register bits TCR2 and TCR3. The
contents of the counter is transferred and an edge interrupt is generated resulting in the
EIRF3 being set.
2.21.1
2.21.2
"star" network configuration or as a co-processor on a "host" processor bus such as an IBM PC or
compatible or an Apple II or Mac II personal computer. This PIB may also be used as part of the file
server system for large memory systems.
Select (low active)/Parallel Interface Chip Select (high active) (PICSB/PICS) signal to transfer data to
and from the Parallel Interface Register selected by the Parallel Interface Register select (PIRSx)
input pins. When PIWEB and PICSB are configured by the Parallel Interface Bus Enable Register bit
1 (PIBER1=0), then the PIB interface is compatible with WDC
operation with the chip select PICSB input. The use of PIWEB and PICS are configured by
PIBER1=1.
2.21.3 The PIB interrupt output to the "host" is generated on the Parallel Interface Interrupt (PII) pin.
The "host" interrupt is suggested to be received on the IRQ level interrupt input pin of the "host"
processor.
The Parallel Interface Bus (PIB) pins are used to communicate between processors in a
The Parallel Interface Write Enable (PIWEB) input pin is used with the Parallel Interface Chip
microprocessor WE- logical
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