IDT72261 IDT [Integrated Device Technology], IDT72261 Datasheet - Page 11

• Manufacturer Part Number: IDT72261
• Description: CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9
• Manufacturer: IDT [Integrated Device Technology]

IDT72261/72271 SyncFIFO
16,384 x 9, 32,768 x 9
equal to or less than the cycle period of the non-selected
clock.
permissible to stop the non-selected clock. Note, so long as
RCLK is idle,
as long as WCLK is idle,
ing or writing) is not permitted; however, such a change at the
time of Master Reset or Partial Reset is all right. FS is an
asynchronous input.
OUTPUTS:
FULL FLAG (
Flag (
write pointer catches up to the read pointer),
inhibiting further write operation. When
is not full. If no reads are performed after a reset (either
or
and 32,768 writes to the IDT72271.
goes LOW when memory space is available for writing in
data. When there is no longer any free space left,
HIGH, inhibiting further write operation. If no reads are
performed after a reset (either
after 16,385 writes for the IDT72261 and 32,769 writes for the
IDT72271.
NOTE:
1. Any bits of the offset register not being programmed should be set to zero.
8
8
8
8
In FWFT Mode, the Input Ready (
PRS
The selected clock must be continuous. It is, however,
Changing the FS setting during FIFO operation (i.e. read-
This is a dual purpose pin. In IDT Standard Mode, the Full
FF
),
) function is selected. When the FIFO is full (i.e. the
FF
will go LOW after 16,384 writes tor the IDT72261
EF
5
FF FF
5
7
7
/
/
OR
IR IR
72261 – 16,384 x 9–BIT
)
and
3FFH if
3FFH if
EMPTY OFFSET (MSB) REG.
07FH if
EMPTY OFFSET (LSB) REG.
07FH if
FULL OFFSET (LSB) REG.
FULL OFFSET (MSB) REG.
PAE
FF
/
IR
will not be updated. Likewise,
MRS
LD
LD
LD
and
LD
DEFAULT VALUE
DEFAULT VALUE
00H
00H
IR
is HIGH at Master Reset
is HIGH at Master Reset
is LOW at Master Reset
is LOW at Master Reset
PAF
) function is selected.
or
PRS
FF
Figure 3. Offset Register Location and Default Values
will not be updated.
is HIGH, the FIFO
),
FF
IR
will go LOW,
will go HIGH
3036 drw 05
IR
goes
MRS
IR
0
0
0
0
memory, but also counts the presence of a word in the output
register. Thus, in FWFT mode, the total number of writes
necessary to deassert
FF
enhance metastable immunity.
EMPTY FLAG (
Empty Flag (
(i.e. the read pointer catches up to the write pointer),
LOW, inhibiting further read operations. When
the FIFO is not empty.
time of
Latency parameter, t
WCLK edge that writes the first word to the rising RCLK edge
that updates the flag. t
skew and can be expressed as follows:
where T
is shorter, and T
take place until
how early the first word can be available at Q
no effect on the reading of subsequent words.
8
8
8
8
The
FF
This is a dual purpose pin. In the IDT Standard Mode, the
When writing the first word to an empty FIFO, the deassertion
in IDT Standard mode.
/
IR
IR
EF
is synchronized to WCLK. It is double-registered to
f
status not only measures the contents of the FIFO
is either the RCLK or the WCLK period, whichever
is variable, and can be represent by the First Word
MILITARY AND COMMERCIAL TEMPERATURE RANGES
EF
t
6
6
FWL1
7
7
) function is selected. When the FIFO is empty
EF EF
RCLK
EF
72271 – 32,768 x 9–BIT
3FFH if
3FFH if
07FH if
07FH if
/
max. = 10*T
OR
OR
goes HIGH, the t
FWL1
is the RCLK period. Since no read can
IR
FWL1
)
EMPTY OFFSET (LSB) REG.
FULL OFFSET (LSB) REG.
EMPTY OFFSET (MSB) REG.
FULL OFFSET (MSB) REG.
is one greater than needed to assert
LD
, which is measured from the rising
LD
LD
LD
DEFAULT VALUE
DEFAULT VALUE
includes any delays due to clock
is HIGH at Master Reset
is HIGH at Master Reset
is LOW at Master Reset
is LOW at Master Reset
f
00H
00H
+ 2*T
FWL1
RCLK
delay determines
(in ns)
n
. This delay has
EF
3036 drw 06
EF
is HIGH,
will go
11
0
0
0
0