IDT72261 IDT [Integrated Device Technology], IDT72261 Datasheet - Page 9

• Manufacturer Part Number: IDT72261
• Description: CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9
• Manufacturer: IDT [Integrated Device Technology]

IDT72261/72271 SyncFIFO
16,384 x 9, 32,768 x 9
SERIAL ENABLE (
programming of the offset registers. The serial programming
method must be selected during Master Reset.
used in conjunction with
data at the SI input can be loaded into the input register one
bit for each LOW-to-HIGH transition of WCLK.
the previous settings and no offsets are loaded.
FWFT modes.
OUTPUT ENABLE (
output buffers receive data from the output register. When
is HIGH, the output data bus (Q
state.
LOAD (
of the Load line (
or 1023) for the
which these flags can be programmed, parallel or serial. After
NOTES:
1. Only one of the two offset programming methods, serial or parallel, is available for use at any given time.
2. The programming method can only be selected at Master Reset.
3. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
4. The programming sequence applies to both IDT Standard and FWFT modes.
Serial Enable is (
When
SEN
When Output Enable (
This is a dual purpose pin. During Master Reset, the state
LD LD
functions the same way in both IDT Standard and
SEN
)
LD
0
0
0
X
1
1
1
is HIGH, the programmable registers retains
LD
PAE
) determines one of two default values (127
SEN
SEN
and
SEN
OE OE
WEN
)
LD
X
)
0
1
1
1
0
1
PAF
) is an enable used only for serial
OE
. When these lines are both LOW,
) is enabled (LOW), the parallel
flags, along with the method by
n
) goes into a high impedance
REN
X
1
0
1
1
0
1
Figure 2. Partial Flag Programming Sequence
SEN
SEN
1
1
X
X
X
1
0
is always
WCLK
OE
X
X
X
X
Master Reset,
operations from the registers. Only the offset loading method
currently selected can be used to write to the registers. Aside
from Master Reset, there is no other way change the loading
method. Registers can be read only in parallel; this can be
accomplished regardless of whether serial or the parallel
loading has been selected.
PAF
from. Offset values contained in these registers determine
how many words need to be in the FIFO memory to switch a
partial flag. A LOW on
default
the empty boundary), a default
threshold 127 words from the full boundary), and parallel
loading of other offset values. A HIGH on
Reset selects a default
1023 words from the empty boundary), a default
value of 3FFH (a threshold 1023 words form the full bound-
ary), and serial loading of other offset values.
dedicated write offset register pointer. The act of reading
offsets employs a dedicated read offset register pointer. The
Associated with each of the programmable flags,
The act of writing offsets (in parallel or serial) employs a
RCLK
, are two registers which can either be written to or read
X
X
X
X
X
PAE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
offset value of 07FH ( a threshold 127 words from
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Serial shift into registers:
28 bits for the 72261
30 bits for the 72271
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
No Operation
Write Memory
Read Memory
No Operation
Ending with Full Offset (MSB)
LD
enables write operations to and read
PAE
LD
Selection
offset value of 3FFH (a threshold
during Master Reset selects a
PAF
offset value of 07FH (a
3097 tbl 01
LD
during Master
PAF
PAE
offset
and
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