IDT72261 IDT [Integrated Device Technology], IDT72261 Datasheet - Page 22

• Manufacturer Part Number: IDT72261
• Description: CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9
• Manufacturer: IDT [Integrated Device Technology]

IDT72261/72271 SyncFIFO
16,384 x 9, 32,768 x 9
Q0 - Q8
NOTES:
1.
WCLK
RCLK
NOTES:
1.
2. Data in the output register does not count as a "word in FIFO memory". Since, in FWFT mode, the first word written to an empty FIFO goes unrequested
3. t
RCLK
WEN
REN
PAE
OE
REN
PAE
to the output register (no read operation necessary), it is not included in the FIFO memory count.
the rising edge of WCLK and the rising edge of RCLK is less than t
SKEW2
LD
= LOW
offset = n
t
CLKH
n words in FIFO memory
is the minimum time between a rising WCLK edge and a rising RCLK edge for
DATA IN OUTPUT
t
CLKH
REGISTER
t
ENS
t
Figure 13. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT modes)
t
SKEW2
CLK
t
(1,2)
t
LDS
Figure 14. Programmable Almost Empty Flag Timing (IDT Standard and FWFT modes)
ENS
(3)
t
CLKL
t
CLKL
t
ENH
1
t
A
t
t
LDH
ENH
PAE OFFSET
2
t
PAE
(LSB)
SKEW2
, then the
PAE OFFSET
t
ENS
PAE
(MSB)
PAE
to go HIGH (after one RCLK cycle plus t
deassertion may be delayed one extra RCLK cycle.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
n+1 words in FIFO memory
PAF OFFSET
t
ENH
(LSB)
t
1
t
t
A
LDH
ENH
PAE
PAF OFFSET
). If the time between
(MSB)
2
t
PAE
n words
in FIFO
memory
3036 drw 16
3036 drw 17
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