IDT72261 IDT [Integrated Device Technology], IDT72261 Datasheet - Page 24

• Manufacturer Part Number: IDT72261
• Description: CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9
• Manufacturer: IDT [Integrated Device Technology]

IDT72261/72271 SyncFIFO
16,384 x 9, 32,768 x 9
Q
D
WCLK
NOTES:
1. t
2. Retransmit Setup is complete after
3. Following Retransmit Setup, the rising edge of RCLK that accesses the first memory location also initiates the updating of
4. No more than D - 2 words (D = 16,384 words for the 72261, 32,768 words for the 72271) should have been written to the FIFO between Reset (Master
5.
RCLK
WEN
0
REN
0
FF
PAE
PAF
RT
HF
- D
- Q
EF
t
Where T
been met:
or Partial) and Retransmit Setup. Therefore,
OE
(4)
RTF1
RFTF1
8
8
= LOW
contributes a variable delay to the overall retransmit recovery time:
max = 14*T
f
is either the RCLK or the WCLK period, whichever is shorter, and T
EF
W
is HIGH or 14 cycles of the faster clock (RCLK or WCLK) have elapsed since the RCLK rising edge enabled by the
y
t
ENS
f
+ 3*T
t
t
A
ENH
t
t
ENS
DS
RCLK
W
t
t
x
ENH
(in ns)
DH
t
RTS
EF
t
returns HIGH, only then can a read operation begin. Write operations are permitted after one of two conditions have
RTS
t
ENS
t
t
ENH
REF
Figure 17. Retransmit Timing (IDT Standard mode)
FF
will be HIGH throughout the Retransmit Setup procedure.
t
RTF1
(1,2)
t
REF
W
RCLK
t
[y+1]
ENS
t
DS
W
is the RCLK period.
t
[x + 1]
ENS
t
ENH
t
DH
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1
t
t
SKEW2
(3)
t
t
HF
ENH
A
1
W
1
t
2
PAF
2
HF
,
PAE
RT
, and
pulse.
3
PAF
t
PAE
3036 drw 20
.
24