IDT72261 IDT [Integrated Device Technology], IDT72261 Datasheet - Page 27

• Manufacturer Part Number: IDT72261
• Description: CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9
• Manufacturer: IDT [Integrated Device Technology]

IDT72261/72271 SyncFIFO
16,384 x 9, 32,768 x 9
D
Q
WCLK
NOTES:
1. t
2. Retransmit Setup is complete after
3. Following Retransmit Setup, the rising edge of RCLK that accesses the first memory location also initiates the updating of
4. No more than D - 2 words (D = 16,384 words for the 72261, 32,768 words for the 72271) should have been written to the FIFO between Reset (Master
5.
RCLK
WEN
0
REN
0
OR
RT
PAE
PAF
- D
HF
- Q
t
Where T
have been met:
or Partial) and Retransmit Setup. Therefore,
OE
IR
RTF2
RTF2
8
8
(4)
= LOW
max = 14*T
contribute a variable delay to the overall retransmit time:
f
is either the RCLK or the WCLK period, whichever is shorter, and T
W
y
t
ENS
OR
f
+ 4*T
is LOW or 14 cycles of the faster clock (RCLK or WCLK) have elapsed since the RCLK rising edge enabled by the
t
t
ENH
A
RCLK
t
t
ENS
DS
W
(in ns)
t
t
x
ENH
DH
t
RTS
OR
t
t
RTS
ENS
returns LOW, only then can a read operation begin. Write operations are permitted after one of two conditions
t
t
W
ENH
REF
IR
[y+1]
will be LOW throughout the Retransmit Setup procedure.
Figure 20. Retransmit Timing (FWFT mode)
t
RTF1
(1,2)
1
t
t
t
REF
SKEW2
(3)
t
HF
A
1
RCLK
is the RCLK period.
2
t
PAF
MILITARY AND COMMERCIAL TEMPERATURE RANGES
2
t
ENS
t
DS
W
[x + 1]
t
ENH
t
DH
W
1
t
3
PAE
HF
,
PAE
t
ENS
, and
RT
PAF
t
ENH
t
3036 drw 23
pulse.
A
.
27
W
2