IDT72261 IDT [Integrated Device Technology], IDT72261 Datasheet - Page 12

• Manufacturer Part Number: IDT72261
• Description: CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9
• Manufacturer: IDT [Integrated Device Technology]

IDT72261/72271 SyncFIFO
16,384 x 9, 32,768 x 9
OR
empty FIFO appears valid on the outputs.
cycle after RCLK shifts the last word from the FIFO memory
to the outputs. Then further data reads are inhibited until
goes LOW again.
time of
Word Latency parameter, t
rising WCLK edge that writes the first word to the rising RCLK
edge that updates the flag. t
clock skew and can be expressed as follows:
where T
NOTES:
1. Data in the output register does not count as a "word in FIFO memory". Since, in FWFT mode, the first word written to an empty FIFO goes unrequested
2. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n=1023 when serial offset loading is selected.
3. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or n=1023 when serial offset loading is selected.
4. Following a reset (Master or Partial), the FIFO memory is empty and
NOTES:
1. Data in the output register does not count as a "word in FIFO memory". Since, in FWFT mode, the first word written to an empty FIFO goes unrequested
2. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n=1023 when serial offset loading is selected.
3. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or n=1023 when serial offset loading is selected.
TABLE I –– STATUS FLAGS FOR IDT STANDARD MODE
TABLE II –– STATUS FLAGS FOR FWFT MODE
In FWFT Mode, the Ouput Ready (
When writing the first word to an empty FIFO, the assertion
to the output register (no read operation necessary), it is not included in the FIFO memory count.
is placed into the output register, and
a rising RCLK edge, enabled by
to the output register (no read operation necessary), it is not included in the FIFO memory count.
goes LOW at the same time that the first word written to an
8,193 to (16,384-(m+1))
8,193 to (16,384-(m+1))
(16,384-m)
OR
f
(16,384-m)
is either the RCLK or the WCLK period, whichever is
(n+1) to 8,192
(n+1) to 8,192
is variable, and can be represented by the First
t
FWL2
Number of Words in FIFO Memory
1 to n
16,384
72261
1 to n
16,384
72261
0
0
(3)
(3)
max. = 10*T
(2)
to 16,383
(2)
Number of Words in FIFO Memory
to 16,383
FWL2
FWL2
REN
, which is measured from the
f
+ 3*T
, will set
OR
includes any delay due to
OR
goes LOW. In this case, or any time the last word in the FIFO memory has been read into the output register;
16,385 to (32,768-(m+1))
16,385 to (32,768-(m+1))
RCLK
(32,768-m)
(32,768-m)
) function is selected.
OR
OR
(n+1) to16,384
(n+1) to16,384
HIGH.
(in ns)
goes HIGH one
1 to n
32,768
72271
1 to n
32,768
72271
0
0
(3)
(3)
(2)
to 32,767
(1)
(2)
to 32,767
OR
OR
(1)
= HIGH. After writing the first word, the FIFO memory remains empty, the data
shorter, and T
Word Latency in FWFT mode is one RCLK cycle longer than
in IDT Standard mode. The t
the first word can be available at Q
on the reading of subsequent words.
to enhance metastable immunity.
PROGRAMMABLE ALMOST-FULL FLAG (
when the FIFO reaches the Almost-Full condition as specified
by the offset m stored in the Full Offset register.
one of two possible default offset values are chosen. If
The Programmable Almost-Full Flag (
At the time of Master Reset, depending on the state of
EF
/
OR
IR IR
FF FF
L
L
L
L
L
H
H
H
H
H
H
L
is sychronized to the RCLK. It is double-registered
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RCLK
PAF
PAF
PAF
PAF
H
H
H
H
L
L
H
H
H
H
L
L
is the RCLK period. Note that the First
HF HF
FWL2
HF HF
H
H
H
L
L
L
H
H
H
L
L
L
delay determines how early
n
. This delay has no effect
PAE
PAE
PAE
PAE
L
L
H
H
H
H
L
L
H
H
H
H
PAF
PAF
PAF
) will go LOW
3097 tbl 03
OR OR
3097 tbl 04
EF EF
)
H
L
L
L
L
L
L
H
H
H
H
H
(4)
LD
12
LD
is
,