IDT72261 IDT [Integrated Device Technology], IDT72261 Datasheet - Page 4

• Manufacturer Part Number: IDT72261
• Description: CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9
• Manufacturer: IDT [Integrated Device Technology]

IDT72261/72271 SyncFIFO
16,384 x 9, 32,768 x 9
PIN DESCRIPTION
Symbol
D
MRS
PRS
RT
FWFT/SI
WCLK
WEN
RCLK
REN
OE
SEN
LD
FS
FF
EF
PAF
PAE
HF
Q
V
GND
CC
0
0
/
–D
/
–Q
IR
OR
8
8
Data Inputs
Master Reset
Partial Reset
Retransmit
First Word Fall
Through/Serial In
Write Clock
Write Enable
Read Clock
Read Enable
Output Enable
Serial Enable
Load
Frequency Select
Full Flag/
Input Ready
Empty Flag/
Output Ready
Programmable
Almost Full Flag
Programmable
Almost Empty Flag
Half-full Flag
Data Outputs
Power
Ground
Name
I/O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
Data inputs for a 9-bit bus.
MRS
all zeroes. During Master Reset, the FIFO is configured for either FWFT or IDT
Standard Mode, one of two programmable flag default settings, and serial or
parallel programming of the offset settings.
PRS
all zeroes. During Partial Reset,the existing mode (IDT or FWFT), programming
method (serial or parallel), and programmable flag settings are all retained.
Allows data to be resent starting with the first location of FIFO memory.
During Master Reset, selects First Word Fall Through or IDT Standard mode.
After Master Reset, this pin functions as a serial input for loading offset registers
When enabled by
offsets into the programmable registers.
WEN
When enabled by
memory and offsets from the programmable registers.
REN
SEN
During Master Reset,
1023) and determines programming method, serial or parallel. After Master
Reset, this pin enables writing to and reading from the offset registers.
The FS setting optimizes data flow through the FIFO.
In the IDT Standard Mode, the
not the FIFO memory is full. In the FWFT mode, the
indicates whether or not there is space available for writing to the FIFO memory.
In the IDT Standard Mode, the
not the FIFO memory is empty.
OR
PAF
offset m which is store in Almost Full which is stored in the Full Offset register.
goes LOW if the number of free locations in the FIFO memory is less than m.
PAE
which is stored in theEmpty Offset register.
words in the FIFO memory is greater than offset n.
HF
Data outputs for a 9-bit bus.
+5 volt power supply pins.
Ground pins.
OE
indicates whether the FIFO memory is more or less than half-full.
indicates whether or not there is valid data available at the outputs.
controls the output impedance of Q
goes HIGH if the number of free locations in the FIFO memory is more than
initializes the read and write pointers to zero and sets the output register to
goes LOW if the number of words in the FIFO memory is less than offset n
enables RCLK for reading data from the FIFO memory and offset registers.
enables serial loading of programmable flag offsets
initializes the read and write pointers to zero and sets the output register to
enables WCLK for writing data into the FIFO memory and offset registers.
WEN
REN
LD
, the rising edge of RCLK reads data from the FIFO
, the rising edge of WCLK writes data into the FIFO and
selects one of two partial flag default offsets (127 and
Description
EF
FF
MILITARY AND COMMERCIAL TEMPERATURE RANGES
In FWFT mode, the
function is selected.
function is selected.
n
PAE
goes HIGH if the number of
IR
OR
function is selected.
FF
EF
indicates whether or
indicates whether or
function is selected.
3097 tbl 01
PAF
4
IR