IDT72261 IDT [Integrated Device Technology], IDT72261 Datasheet - Page 8

• Manufacturer Part Number: IDT72261
• Description: CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9
• Manufacturer: IDT [Integrated Device Technology]

IDT72261/72271 SyncFIFO
16,384 x 9, 32,768 x 9
same time, the contents of the first location are automatically
displayed on the outputs. Since FWFT Mode is selected, the
first word appears on the outputs, no read request necessary.
Reading all subsequent words requires a LOW on
enable the rising edge of RCLK. Writing operations can begin
after one of two conditions have been met:
cycles of the faster clock (RCLK or WCLK) have elapsed since
the RCLK rising edge enabled by the
variable. The parameter t
rising RCLK edge enabled by
described by the following equation:
is shorter, and T
Retransmit Setup in FWFT mode requires one more RCLK
cycle than in IDT Standard mode.
are allowed between a Reset and a Retransmit Setup,
remain LOW throughout the setup procedure.
begins with the "last" rising edge of RCLK before the end of
Retransmit Setup. This is the same edge that asserts
automatically accesses the first memory location. Note that,
in this case,
is updated on the "last" RCLK rising edge.
after two more rising RCLK edges.
"last" rising RCLK edge, followed by the next two rising WCLK
edges. (If the t
WCLK cycle.)
useful in the event of a transmission error on a network, since
it allows a data packet to be resent.
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
of the FWFT/SI helps determine whether the device will
operate in IDT Standard mode or First Word Fall Through
(FWFT) mode.
Standard mode will be selected. This mode uses the Empty
Flag (
present in the FIFO memory. It also uses the Full Flag function
(
space for writing. In IDT Standard mode, every word read
from the FIFO, including the first, must be requested using the
Read Enable (
FWFT mode will be selected. This mode uses Output Ready
(
outputs (Q
or not the FIFO memory has any free space for writing. In the
FWFT mode, the first word written to an empty FIFO goes
directly to Q
must be accessed using the Read Enable (
FF
OR
RT
When
where T
Regarding
For FWFT mode, updating the
This is a dual purpose pin. During Master Reset, the state
If, at the time of Master Reset, FWFT/SI is LOW, then IDT
If, at the time of Master Reset, FWFT/SI is HIGH, then
) to indicate whether or not the FIFO memory has any free
) to indicate whether or not there is valid data at the data
The assertion time of
is synchronized to RCLK. The Retransmit operation is
EF
) to indicate whether or not there are any words
OR
n)
f
is either the RCLK or the WCLK period, whichever
n
. It also uses Input Ready (
REN
, no read request necessary. Subsequent words
goes LOW, Retransmit Setup is complete; at the
t
RTF2
IR
REN
skew2
: Note that since no more than Full - 2 writes
is not required to initiate flag updating.
RCLK
max. = 14*T
) line.
specification is not met, add one more
is the RCLK period. Note that a
RTF2
OR
RT
, which is measured from the
f
during Retransmit Setup is
+ 4*T
to the falling edge of
PAE
PAF
RT
RCLK
IR
,
) to indicate whether
is updated after the
HF
pulse.
OR
REN
(in ns)
, and
PAE
is LOW or 14
) line.
is updated
PAF
OR
REN
IR
OR
flags
and
will
HF
to
is
loading
The serial input function can only be used when the serial
loading method has been selected during Master Reset.
FWFT/SI functions the same way in both IDT Standard and
FWFT modes.
WRITE CLOCK (WCLK)
(WCLK). Data set-up and hold times must be met with respect
to the LOW-to-HIGH transition of the WCLK. The write and
read clocks lines can either be asynchronous or coincident.
WRITE ENABLE (
the input register on the rising edge of every WCLK cycle.
Data is stored in the RAM array sequentially and indepen-
dently of any on-going read operation.
data and no new data is loaded into the FIFO.
go LOW , inhibiting further write operations. Upon the comple-
tion of a valid read cycle,
occur.
HIGH, inhibiting further write operations. Upon the completion
of a valid read cycle,
READ CLOCK (RCLK)
read clock (RCLK), when Output Enable (
write and read clocks can be asynchronous or coincident.
READ ENABLE (
RAM array into the output register on the rising edge of the
RCLK.
data and no new data is loaded into the output register.
including the first word written to an empty FIFO, must be
requested using
the FIFO, the Empty Flag (
read operations.
Once a write is performed,
and a read is permitted.
automatically goes to the outputs Q
request. In order to access all other words, a read must be
executed using
the FIFO, Output Ready (
read operations.
Once a write is performed,
when the first word appears at Q
into the FIFO, then
After Master Reset, FWFT/SI acts as a serial input for
A write cycle is initiated on the rising edge of the write clock
When Write Enable (
When
To prevent data overflow in the IDT Standard Mode,
To prevent data overflow in the FWFT mode,
WEN
Data can be read on the outputs, on the rising edge of the
When Read Enable (
When
In the IDT Standard Mode, every word accessed at Q
In the FWFT Mode, the first word written to an empty FIFO
WEN
PAE
is ignored when the FIFO is full.
REN
WEN
MILITARY AND COMMERCIAL TEMPERATURE RANGES
and
is ignored when the FIFO is full.
is HIGH, the output register holds the previous
is HIGH, the input register holds the previous
REN
PAF
REN
REN
REN
REN
REN
WEN
WEN
REN
IR
. When all the data has been read from
offsets into the programmable registers.
. When all the data has been read from
)
WEN
will go LOW allowing a write to occur.
REN
is ignored when the FIFO is empty.
is ignored when the FIFO is empty.
)
can be used to read it out.
OR
FF
EF
OR
EF
) is LOW, data can be loaded into
) is LOW, data is loaded from the
will go HIGH allowing a write to
) will go HIGH, inhibiting further
) will go LOW, inhibiting further
will go HIGH after t
will go LOW after t
n
; if a second word is written
n
, no need for any read
OE
) is set LOW. The
FWL2
IR
FWL1
FF
will go
+t
+t
8
REF,
REF
will
n
,