IDT72261 IDT [Integrated Device Technology], IDT72261 Datasheet - Page 29

• Manufacturer Part Number: IDT72261
• Description: CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9
• Manufacturer: IDT [Integrated Device Technology]

IDT72261/72271 SyncFIFO
16,384 x 9, 32,768 x 9
NOTE:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
requiring more than 16,384/32,768 words of buffering. In
FWFT mode, the FIFOs can be arranged in series (the data
outputs of one FIFO connected to the data inputs of the next)–
no external logic necessary. The resulting configuration
provides a total depth equivalent to the sum of the depths
associated with each single FIFO. Figure 23 shows a depth
expansion using two IDT72261/72271s.
Reset for all FIFOs in the depth expansion configuration. The
WRITE CLOCK
WRITE ENABLE
INPUT READY
DATA BUS
DEPTH EXPANSION CONFIGURATION
The IDT72261/72271 can easily be adapted to applications
Care should be taken to select FWFT mode during Master
GATE
FIRST WORD FALL THROUGH/
(1)
SERIAL INPUT (FWFT/SI)
9
MASTER RESET (
PARTIAL RESET (
FULL FLAG/INPUT READY (
FULL FLAG/INPUT READY (
DATA IN (Dn)
RETRANSMIT (
WEN
IR
Dn
WCLK
FREQUENCY SELECT (FS)
PROGRAMMABLE (
WRITE CLOCK (WCLK)
WRITE ENABLE (
HALF FULL FLAG (
MRS
PRS
Figure 22. Block Diagram of 16,384x18/32,768x18 72261/71 Width Expansion
RT
Figure 23. Block Diagram of 32,768x9/65,536x9 Synchronous FIFO Memory
)
)
)
72261/
72271
FS
18
With Programmable Flags used in Depth Expansion Configuration
LOAD (
FF
FF
/
/
WEN
IR
IR
PAF
9
LD
)
) #2
TRANSFER CLOCK
HF
RCLK
#1
)
)
)
)
REN
OR
OE
Qn
72261/
72271/
IDT
#1
9
•
GND
9
first word written to an empty configuration will pass from one
FIFO to the next ("ripple down") until it finally appears at the
outputs of the last FIFO in the chain–no read operation is
necessary. Each time the data word appears at the outputs
of one FIFO, that device's
to the next FIFO in line.
help of the t
caused by clock skew:
9
The
72261/
72271/
IDT
#2
OR
assertion time is variable and is described with the
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FWL2
READ CLOCK (RCLK)
READ ENABLE (
OUTPUT ENABLE (
EMPTY FLAG/OUTPUT READY (
EMPTY FLAG/OUTPUT READY (
PROGRAMMABLE (
WEN
IR
Dn
WCLK
9
t
FWL2
parameter, which includes including delay
DATA OUT (Qn)
max.= 10*T
72261/
72271
OR
REN
FS
OE
PAE
line goes LOW, enabling a write
)
)
)
18
f
RCLK
+ 3*T
REN
OR
OE
Qn
EF
EF
/
/
OR
OR
RCLK
READ CLOCK
READ ENABLE
OUTPUT READY
OUTPUT ENABLE
DATA OUT
) #2
) #1
3036 drw 25
9
3097 drw 25
3036 drw 26
GATE
(1)
29