IDT72261 IDT [Integrated Device Technology], IDT72261 Datasheet - Page 7

• Manufacturer Part Number: IDT72261
• Description: CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9
• Manufacturer: IDT [Integrated Device Technology]

IDT72261/72271 SyncFIFO
16,384 x 9, 32,768 x 9
SIGNAL DESCRIPTIONS:
INPUTS:
DATA IN (D
CONTROLS:
MASTER RESET (
Reset (
the internal read and write pointers to the first location of the
RAM array.
go HIGH.
Mode, along with
FF
through Mode (FWFT), along with
OR
threshold 127 words from the empty boundary and
assigned a threshold 127 words from the full boundary; 127
words corresponds to an offset value of 07FH. Following
Master Reset, parallel loading of the offsets is permitted, but
not serial loading.
threshold 1023 words from the empty boundary and
assigned a threshold 1023 words from the full boundary;
1023 words corresponds to an offset value of 3FFH. Following
Master Reset, serial loading of the offsets is permitted, but not
parallel loading.
been selected, parallel reading of the registers is always
permitted. (See section describing the
details).
all zeroes. A Master Reset is required after power up, before
a write operation can take place.
PARTIAL RESET (
Reset (
the Master Reset, the internal read and write pointers are set
to the first location of the RAM array,
goes HIGH, and
Standard Mode or First Word Fall-through, that mode will
remain selected. If the IDT Standard Mode is active, then
will go HIGH and
Mode is active, then
ters remain unchanged. The programming method (parallel
or serial) currently active at the time of Partial Reset is also
retained. The output register is initialized to all zeroes.
is asynchronous.
If
Regardless of whether serial or parallel offset loading has
Whichever mode is active at the time of partial reset, IDT
If
If FWFT is LOW during Master Reset then the IDT Standard
Data inputs for 9-bit wide data.
A Master Reset is accomplished whenever the Master
During a Master Reset, the output register is initialized to
A Partial Reset is accomplished whenever the Partial
Following Partial Reset, all values held in the offset regis-
will go HIGH. If FWFT is HIGH, then the First Word Fall
LD
LD
will go HIGH and
is LOW during Master Reset, then
MRS
is HIGH during Master Reset, then
PRS
) input is taken to a LOW state. As in the case of
) input is taken to a LOW state. This operation sets
0
PAE
- D
EF
8
will go LOW,
EF
HF
)
MRS
MRS
PRS
PRS
will go LOW. If the First word Fall-through
and
OR
goes HIGH.
IR
)
)
will go LOW.
FF
will go HIGH, and
are selected.
PAF
MRS
IR
will go HIGH, and
and
PAE
is asynchronous.
EF
LD
PAE
PAE
OR
goes LOW,
IR
will go LOW and
line for further
, are selected.
will go LOW.
is assigned a
is assigned a
PAF
PAF
HF
PRS
PAF
will
FF
is
is
course of operation, when reprogramming flag settings may
not be convenient.
RETRANSMIT (
been read to be accessed again. There are two stages: first,
a setup procedure that resets the read pointer to the first
location of memory, then the actual retransmit, which consists
of reading out the memory contents, starting at the beginning
of memory.
rising RCLK edge.
bringing
2 words should have been written into the FIFO between
Reset (Master or Partial) and the time of Retransmit Setup
(Full = 16,384 words for the 72261, 32,768 words for the
72271).
beginning of the Retransmit Setup by setting
change in level will only be noticeable if
setup. During this period, the internal read pointer is initialized
to the first location of the RAM array.
read operations may begin starting with the first location in
memory. Since IDT Standard Mode is selected, every word
read including the first word following Retransmit Setup re-
quires a LOW on
Writing operations can begin after one of two conditions have
been met:
or WCLK) have elapsed since the RCLK rising edge enabled
by the
variable. The parameter t
rising RCLK edge enabled by
described by the following equation:
where T
shorter, and T
are allowed between a Reset and a Retransmit Setup,
remain HIGH throughout the setup procedure.
flags begins with the "first"
following the end of Retransmit Setup (the point at which
goes HIGH). This same RCLK rising edge is used to access
the "first" memory location.
rising edge.
edges.
followed by the next two rising WCLK edges. (If the t
specification is not met, add one more WCLK cycle.)
of the Retransmit Setup by setting
level will only be noticeable if
During this period, the internal read pointer is set to the first
location of the RAM array.
Regarding
A Partial Reset is useful for resetting the device during the
The Retransmit operation allows data that has already
Retransmit Setup is initiated by holding
If IDT Standard mode is selected, the FIFO will mark the
When
For IDT Standard mode, updating the
If FWFT mode is selected, the FIFO will mark the beginning
The deassertion time of
RT
f
RT
is either the RCLK or the WCLK period, whichever is
EF
PAF
pulse.
EF
MILITARY AND COMMERCIAL TEMPERATURE RANGES
LOW. At least one word, but no more than Full -
goes HIGH, Retransmit Setup is complete and
FF
t
is HIGH or 14 cycles of the faster clock (RCLK
RTF1
RCLK
PAE
is updated after the "first" rising RCLK edge,
: Note that since no more than Full - 2 writes
RT RT
REN
)
max. = 14*T
is updated after two more rising RCLK
is the RCLK period.
REN
to enable the rising edge of RCLK.
RTF1
and
REN
HF
EF
RT
, which is measured from the
OR
f
is updated on the first RCLK
WEN
-enabled rising RCLK edge
+ 3*T
during Retransmit Setup is
to the rising edge of
OR
was LOW before setup.
must be HIGH before
RCLK
HIGH. The change in
EF
PAE
RT
was HIGH before
(in ns)
EF
,
LOW during a
HF
LOW. The
, and
FF
skew2
EF
PAF
7
will
EF
is