IDT72275 IDT [Integrated Device Technology], IDT72275 Datasheet - Page 10

• Manufacturer Part Number: IDT72275
• Manufacturer: IDT [Integrated Device Technology]

IDT72275/72285 SUPERSYNC FIFO™
32,768 x 18, 65,536 x 18
SERIAL PROGRAMMING MODE
scribed above, then programming of
be achieved by using a combination of the
and SI input pins. Programming
follows: when
are written, one bit for each WCLK rising edge, starting with
the Empty Offset LSB and ending with the Full Offset MSB. A
total of 30 bits for the IDT72275 and 32 bits for the IDT72285.
See Figure 13, Serial Loading of Programmable Flag Regis-
ters , for the timing diagram for this mode.
programmed selectively.
status only after the complete set of bits (for all offset regis-
ters) has been entered. The registers can be reprogrammed
as long as the complete set of new offset bits is entered.
When
registers can occur.
the serial programming sequence. In this case, the program-
ming of all offset bits does not have to occur at once. A select
number of bits can be written to the SI input and then, by
bringing
memory via D
with
sequence is written to the registers via SI. If an interruption
of serial programming is desired, it is sufficient either to set
LOW and deactivate
LD
offset programming continues.
partial flag will be valid until the full set of bits required to fill all
the offset registers has been written. Measuring from the
rising WCLK edge that achieves the above criteria;
valid after two more rising WCLK edges plus t
valid after the next two rising RCLK edges plus t
t
mode.
PARALLEL MODE
described above, then programming of
be achieved by using a combination of the
Dn input pins. Programming
when
written into the Empty Offset Register on the first LOW-to-HIGH
transition of WCLK. Upon the second LOW-to-HIGH transition of
WCLK, data are written into the Full Offset Register. The third
transition of WCLK writes, once again, to the Empty Offset
Register. See Figure 14, Parallel Loading of Programmable
Flag Registers , for the timing diagram for this mode.
write offset register pointer. The act of reading offsets em-
ploys a dedicated read offset register pointer. The two point-
ers operate independently; however, a read and a write
should not be performed simultaneously to the offset regis-
ters. A Master Reset initializes both pointers to the Empty
SKEW2
If Serial Programming mode has been selected, as de-
Using the serial method, individual registers cannot be
Write operations to the FIFO are allowed before and during
. Once
From the time serial programming has begun, neither
It is not possible to read the flag offset values in a serial
If Parallel Programming mode has been selected, as
The act of writing offsets in parallel employs a dedicated
LD
LD
LD
.
and
LD
and
LD
is LOW and
and
SEN
and
n
WEN
LD
by toggling
SEN
SEN
and
restored to a LOW, the next offset bit in
are set LOW, data on the inputs Dn are
SEN
SEN
are both restored to a LOW level, serial
HIGH, data can be written to FIFO
SEN
WEN
or to set
PAE
are set LOW, data on the SI input
PAE
is HIGH, no serial write to the
. When
and
and
PAE
SEN
PAE
PAF
PAE
PAF
and
WEN
LD
LOW and deactivate
and
proceeds as follows:
and
can show a valid
, WCLK ,
PAF
LD
is brought HIGH
PAF
PAF
PAF
,
proceeds as
SEN
,
PAE
values can
PAF
values can
PAE
WEN
, WCLK
will be
will be
plus
and
LD
Offset (LSB) register. A Partial Reset has no effect on the
position of these pointers.
the parallel programming sequence. In this case, the pro-
gramming of all offset registers does not have to occur at one
time. One, two or more offset registers can be written and then
by bringing
FIFO memory. When
the next offset register in sequence is written to. As an
alternative to holding
programming can also be interrupted by setting
toggling
invalid during the programming process. From the time
parallel programming has begun, a partial flag output will not
be valid until the appropriate offset word has been written to
the register(s) pertaining to that flag. Measuring from the rising
WCLK edge that achieves the above criteria;
after two more rising WCLK edges plus t
after the next two rising RCLK edges plus t
read offset register pointer. The contents of the offset regis-
ters can be read on the Q
REN
Register on the first LOW-to-HIGH transition of RCLK. Upon
the second LOW-to-HIGH transition of RCLK, data are read
from the Full Offset Register. The third transition of RCLK
reads, once again, from the Empty Offset Register. See
Figure 15, Parallel Read of Programmable Flag Registers , for
the timing diagram for this mode.
quence with reads or writes to the FIFO. The interruption is
accomplished by deasserting
When
offset registers continues where it left off. It should be noted,
and care should be taken from the fact that when a parallel
read of the flag offsets is performed, the data word that was
present on the output lines Qn will be overwritten.
regardless of which timing mode (IDT Standard or FWFT
modes) has been selected.
RETRANSMIT OPERATION
been read to be accessed again. There are two stages: first,
a setup procedure that resets the read pointer to the first
location of memory, then the actual retransmit, which consists
of reading out the memory contents, starting at the beginning
of memory.
rising RCLK edge.
bringing
words should have been written into the FIFO between Reset
(Master or Partial) and the time of Retransmit setup. D = 32,768
for the IDT72275 and D = 65,536 for the IDT72285. In FWFT
mode, D = 32,769 for the IDT72275 and D= 65,537 for the
IDT72285.
beginning of the Retransmit setup by setting
Write operations to the FIFO are allowed before and during
Note that the status of a partial flag (
The act of reading the offset registers employs a dedicated
It is permissible to interrupt the offset register read se-
The Retransmit operation allows data that has already
Retransmit setup is initiated by holding
If IDT Standard mode is selected, the FIFO will mark the
Parallel reading of the offset registers is always permitted
is set LOW. Data are read via Q
REN
WEN
RT
LD
and
LOW. At least one word, but no more than D - 2
.
HIGH, write operations can be redirected to the
LD
are restored to a LOW level, reading of the
REN
LD
WEN
is set LOW again, and
0
COMMERCIAL TEMPERATURE RANGE
-Q
and
LOW and toggling
n
pins when
REN
WEN
,
n
must be HIGH before
LD
from the Empty Offset
PAE
PAF
, or both together.
LD
RT
,
PAE
or
PAE
PAF
is set LOW and
EF
PAF
LOW during a
WEN
LD
plus t
LD
will be valid
will be valid
LOW. The
) output is
LOW and
, parallel
is LOW,
SKEW2
10
.