IDT72275 IDT [Integrated Device Technology], IDT72275 Datasheet - Page 13

• Manufacturer Part Number: IDT72275
• Manufacturer: IDT [Integrated Device Technology]

IDT72275/72285 SUPERSYNC FIFO™
32,768 x 18, 65,536 x 18
WRITE CLOCK (WCLK)
input. Data setup and hold times must be met with respect to
the LOW-to-HIGH transition of the WCLK. It is permissible to
stop the WCLK. Note that while WCLK is idle, the
and
capable of updating
Clocks can either be independent or coincident.
WRITE ENABLE (
FIFO RAM array on the rising edge of every WCLK cycle if the
device is not full. Data is stored in the RAM array sequentially
and independently of any ongoing read operation.
array on each WCLK cycle.
go LOW, inhibiting further write operations. Upon the comple-
tion of a valid read cycle,
occur. The
the RCLK cycle.
HIGH, inhibiting further write operations. Upon the completion
of a valid read cycle,
The
valid RCLK cycle.
Standard mode.
READ CLOCK (RCLK)
input. Data can be read on the outputs, on the rising edge of
the RCLK input. It is permissible to stop the RCLK. Note that
while RCLK is idle, the
updated. (Note that RCLK is only capable of updating the
flag to HIGH.) The Write and Read Clocks can be indepen-
dent or coincident.
READ ENABLE (
array into the output register on the rising edge of every RCLK
cycle if the device is not empty.
previous data and no new data is loaded into the output register.
The data outputs Q
including the first word written to an empty FIFO, must be
requested using
the FIFO, the Empty Flag (
read operations.
Once a write is performed,
occur. The
after the valid WCLK cycle.
automatically goes to the outputs Q
to HIGH transition of RCLK + t
does not need to be asserted LOW. In order to access all other
words, a read must be executed using
A write cycle is initiated on the rising edge of the WCLK
When the
When
To prevent data overflow in the IDT Standard mode,
To prevent data overflow in the FWFT mode,
WEN
A read cycle is initiated on the rising edge of the RCLK
When Read Enable is LOW, data is loaded from the RAM
When the
In the IDT Standard mode, every word accessed at Q
In the FWFT mode, the first word written to an empty FIFO
IR
HF
flag is updated by two WCLK cycles + t
flags will not be updated. (Note that WCLK is only
is ignored when the FIFO is full in either FWFT or IDT
WEN
FF
EF
WEN
REN
is updated by two WCLK cycles + t
is HIGH, no new data is written in the RAM
flag is updated by two RCLK cycles + t
REN
REN
REN
REN
REN
REN
input is HIGH, the output register holds the
REN
WEN
WEN
WEN
input is LOW, data may be loaded into the
WEN
WEN
0
-Q
IR
HF
. When the last word has been read from
)
n
will go LOW allowing a write to occur.
EF
is ignored when the FIFO is empty.
)
maintain the previous data value.
flag to LOW.) The Write and Read
FF
/
EF
EF
OR
will go HIGH allowing a write to
) will go LOW, inhibiting further
will go HIGH allowing a read to
SKEW
,
PAE
n
after the first write.
and
, on the third valid LOW
REN
HF
. The RCLK LOW
flags will not be
SKEW
FF
SKEW
IR
after the
/
IR
will go
FF
,
SKEW
after
REN
PAF
will
HF
n
,
to HIGH transition after the last word has been read from the
FIFO, Output Ready (
with
ignored when the FIFO is empty.
SERIAL ENABLE (
ming of the offset registers. The serial programming method
must be selected during Master Reset.
in conjunction with
at the SI input can be loaded into the program register one bit
for each LOW-to-HIGH transition of WCLK. (See Figure 4.)
the previous settings and no offsets are loaded.
the same way in both IDT Standard and FWFT modes.
OUTPUT ENABLE (
buffers receive data from the output register. When
the output data bus (Q
LOAD (
the
1,023) for the
these offset registers can be programmed, parallel or serial.
After Master Reset,
operations from the offset registers. Only the offset loading
method currently selected can be used to write to the registers.
Offset registers can be read only in parallel. A LOW on
Master Reset selects a default
threshold 127 words from the empty boundary), a default
offset value of 07FH (a threshold 127 words from the full
boundary), and parallel loading of other offset values. A HIGH
on
3FFH (a threshold 1,023 words from the empty boundary), a
default
the full boundary), and serial loading of other offset values.
programming process of the flag offset values
Pulling
read of these offset values. See Figure 4, Programmable Flag
Offset Programming Sequence .
OUTPUTS:
FULL FLAG (
Flag (
LOW, inhibiting further write operations. When
FIFO is not full. If no reads are performed after a reset (either
MRS
(D = 32,768 for the IDT72275 and 65,536 for the IDT72285).
See Figure 7, Write Cycle and Full Flag Timing (IDT Standard
Mode) , for the relevant timing information.
IR
data. When there is no longer any free space left,
goes LOW when memory space is available for writing in
The
When
When Output Enable is enabled (LOW), the parallel output
This is a dual purpose pin. During Master Reset, the state of
LD
After Master Reset, the
This is a dual purpose pin. In IDT Standard mode, the Full
In FWFT mode, the Input Ready (
LD
REN
or
FF
during Master Reset selects a default
input determines one of two default offset values (127 or
PAF
SEN
LD
LD LD LD LD LD
) function is selected. When the FIFO is full,
PRS
SEN
= LOW), inhibiting further read operations.
)
LOW will begin a serial loading or parallel load or
offset value of 3FFH (a threshold 1,023 words from
input is an enable used only for serial program-
PAE
),
FF FF FF FF FF
is HIGH, the programmable registers retains
FF
/
and
IR IR IR IR IR
LD
will go LOW after D writes to the FIFO
)
SEN
SEN
SEN
SEN
SEN
LD
OE OE
OE OE
OE
OR
PAF
. When these lines are both LOW, data
n
) goes into a high impedance state.
enables write operations to and read
)
)
) will go HIGH with a true read (RCLK
flags, along with the method by which
COMMERCIAL TEMPERATURE RANGE
LD
PAE
pin is used to activate the
offset value of 07FH (a
IR
) function is selected.
SEN
PAE
is always used
FF
PAE
SEN
offset value of
is HIGH, the
OE
LD
functions
and
FF
is HIGH,
IR
REN
during
will go
13
goes
PAF
PAF
is
.