IDT72275 IDT [Integrated Device Technology], IDT72275 Datasheet - Page 24

• Manufacturer Part Number: IDT72275
• Manufacturer: IDT [Integrated Device Technology]

IDT72275/72285 SUPERSYNC FIFO™
32,768 x 18, 65,536 x 18
OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
gether the control signals of multiple devices. Status flags can
be detected from any one device. The exceptions are the
and
functions in FWFT mode. Because of variations in skew
between RCLK and WCLK, it is possible for
and
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
DEPTH EXPANSION CONFIGURATION (FWFT MODE
ONLY)
ing depths greater than 32,768 and 65,536 for the IDT72285
with an 18-bit bus width. In FWFT mode, the FIFOs can be
connected in series (the data outputs of one FIFO connected
to the data inputs of the next) with no external logic necessary.
The resulting configuration provides a total depth equivalent
to the sum of the depths associated with each single FIFO.
Figure 24 shows a depth expansion using two IDT72275/
72285 devices.
Reset for all FIFOs in the depth expansion configuration. The
first word written to an empty configuration will pass from one
FIFO to the next ("ripple down") until it finally appears at the
The IDT72275 can easily be adapted to applications requir-
Care should be taken to select FWFT mode during Master
Word width may be increased simply by connecting to-
IR
FF
GATE
/
OR
functions in IDT Standard mode and the
(1)
FIRST WORD FALL THROUGH/
DATA IN
assertion to vary by one cycle between FIFOs. In
SERIAL INPUT (FWFT/SI)
MASTER RESET (
PARTIAL RESET (
FULL FLAG/INPUT READY (
FULL FLAG/INPUT READY (
RETRANSMIT (
m + n
PROGRAMMABLE (
WRITE CLOCK (WCLK)
WRITE ENABLE (
HALF-FULL FLAG (
Figure 19. Block Diagram of 32,768 x 36 and 65,536 x 36 Width Expansion
)
)
)
D
0
- Dm
LOAD (
/ )
/ ) #2
m
#1
EF
)
)
)
)
/
FF
72275
72285
FIFO
deassertion
IDT
#1
IR
and
Dm
m
OR
+1
EF
- Dn
Q
0
n
- Qm
IDT Standard mode, such problems can be avoided by
creating composite flags, that is, ANDing
and separately ANDing
composite flags can be created by ORing
and separately ORing
IDT72275/72285 devices. D
36-bit wide input bus and Q
bit wide output bus. Any word width can be attained by adding
additional IDT72275/72285 devices.
outputs of the last FIFO in the chain–no read operation is
necessary but the RCLK of each FIFO must be free-running.
Each time the data word appears at the outputs of one FIFO,
that device's
FIFO in line.
it takes for
data to appear on the last FIFO's outputs) after a word has
been written to the first FIFO is the sum of the delays for each
individual FIFO:
where N is the number of FIFOs in the expansion and T
is the RCLK period. Note that extra cycles should be added
for the possibility that the t
For an empty expansion configuration, the amount of time
Figure 23 demonstrates a width expansion using two
72275
72285
FIFO
IDT
#2
OR
OR
READ CLOCK (RCLK)
n
(N – 1)*(4*transfer clock) + 3*T
READ ENABLE (
OUTPUT ENABLE (
EMPTY FLAG/OUTPUT READY (
EMPTY FLAG/OUTPUT READY (
PROGRAMMABLE (
of the last FIFO in the chain to go LOW (i.e. valid
Qm
line goes LOW, enabling a write to the next
+1
- Qn
IR
FF
of every FIFO.
COMMERCIAL TEMPERATURE RANGE
0
of every FIFO. In FWFT mode,
-Q
SKEW3
0
)
- D
17
)
m + n
)
from each device form a 36-
17
from each device form a
specification is not met
DATA OUT
/
/
OR
EF
) #2
) #1
RCLK
of every FIFO,
4674 drw 22
of every FIFO,
GATE
(1)
24
RCLK