IDT72275 IDT [Integrated Device Technology], IDT72275 Datasheet - Page 22

• Manufacturer Part Number: IDT72275
• Manufacturer: IDT [Integrated Device Technology]

IDT72275/72285 SUPERSYNC FIFO™
32,768 x 18, 65,536 x 18
NOTE:
1.
NOTES:
1. m =
2. D = maximum FIFO depth.
3. t
4.
D
Q
WCLK
RCLK
0
OE
WCLK
0
In IDT Standard mode: D = 32,768 for the IDT72275 and 65,536 for the IDT72285.
In FWFT mode: D = 32,769 for the IDT72275 and 65,537 for the IDT72285.
time between the rising edge of RCLK and the rising edge of WCLK is less than t
PAF
SKEW2
RCLK
- D
- Q
= LOW
15
15
PAF
is asserted and updated on the rising edge of WCLK only.
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
t
CLKH
offset .
Figure 14. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
ENS
Figure 15. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
Figure 16. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
D - (m+1) words in FIFO
t
CLKL
t
ENH
DATA IN OUTPUT
t
REGISTER
CLKH
t
CLKH
1
(2)
t
CLK
t
CLK
t
t
ENS
LDS
t
t
CLKL
DS
t
ENS
t
LDS
t
CLKL
OFFSET
PAE
2
t
PAF
t
t
t
ENH
DH
SKEW2
LDH
t
LDH
t
t
ENH
A
t
ENS
, then the
t
SKEW2
(3)
PAF
OFFSET
PAF
PAF
deassertion time may be delayed one extra WCLK cycle.
t
ENH
D - m words in FIFO
will go HIGH (after one WCLK cycle plus t
OFFSET
PAE
t
DH
t
t
1
ENH
LDH
t
t
COMMERCIAL TEMPERATURE RANGE
ENH
LDH
t
A
(2)
2
t
PAF
OFFSET
PAF
D-(m+1) words
in FIFO
4674 drw 17
4674 drw 19
4674 drw 18
PAF
( 2)
). If the
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