IDT72275 IDT [Integrated Device Technology], IDT72275 Datasheet - Page 25

• Manufacturer Part Number: IDT72275
• Manufacturer: IDT [Integrated Device Technology]

IDT72275/72285 SUPERSYNC FIFO™
32,768 x 18, 65,536 x 18
between WCLK and transfer clock, or RCLK and transfer
clock, for the
written to an empty depth expansion configuration. There will
be no delay evident for subsequent words written to the
configuration.
expansion configuration will "bubble up" from the last FIFO to
the previous one until it finally moves into the first FIFO of the
chain. Each time a free location is created in one FIFO of the
chain, that FIFO's
FIFO to write a word to fill it.
takes for
ORDERING INFORMATION
NOTE:
1. Industrial temperature range is available by special order.
IDT
The "ripple down" delay is only noticeable for the first word
The first free location created by reading from a full depth
For a full expansion configuration, the amount of time it
FWFT/SI
WRITE CLOCK
WRITE ENABLE
INPUT READY
DATA IN
Device Type
XXXXX
IR
of the first FIFO in the chain to go LOW after a word
n
OR
flag.
IR
Power
line goes LOW, enabling the preceding
Dn
WCLK
X
Figure 20. Block Diagram of 65,536 x 18 and 131,072 x 18 Depth Expansion
FWFT/SI
Speed
72275
72285
XX
IDT
•
TRANSFER CLOCK
Package
RCLK
Qn
X
Temperature
Process /
Range
•
GND
X
n
has been read from the last FIFO is the sum of the delays for
each individual FIFO:
where N is the number of FIFOs in the expansion and T
is the WCLK period. Note that extra cycles should be added
for the possibility that the t
between RCLK and transfer clock, or WCLK and transfer
clock, for the
RCLK, whichever is faster. Both these actions result in data
moving, as quickly as possible, to the end of the chain and free
locations to the beginning of the chain.
The Transfer Clock line should be tied to either WCLK or
BLANK
PF
TF
10
15
20
L
72275
72285
WCLK
Dn
IR
(N – 1)*(3*transfer clock) + 2 T
flag.
Commercial
Commercial (0 C to +70 C)
Thin Plastic Quad Flatpack (TQFP, PN64-1)
Slim Thin Quad Flatpack (STQFP, PP64-1)
Low Power
32,768 x 18 SuperSyncFIFO
65,536 x 18 SuperSyncFIFO
FWFT/SI
72275
72285
IDT
COMMERCIAL TEMPERATURE RANGE
SKEW1
Clock Cycle Time (t
Speed in Nanoseconds
RCLK
specification is not met
Qn
OUTPUT ENABLE
n
OUTPUT READY
READ ENABLE
WCLK
READ CLOCK
DATA OUT
4674 drw 23
4674 drw 24
CLK
)
25
WCLK