IDT72275 IDT [Integrated Device Technology], IDT72275 Datasheet - Page 17

• Manufacturer Part Number: IDT72275
• Manufacturer: IDT [Integrated Device Technology]

NOTES:
1. t
2.
IDT72275/72285 SUPERSYNC FIFO™
32,768 x 18, 65,536 x 18
NOTES:
1. t
2.
Q
D
Q
D
WCLK
WCLK
RCLK
0
0
0
0
RCLK
If the time between the rising edge of WCLK and the rising edge of RCLK is less than t
LD
If the time between the rising edge of the RCLK and the rising edge of the WCLK is less than t
extra WCLK cycle.
LD
SKEW3
- Q
- D
- D
- Q
SKEW1
= HIGH
n
n
n
= HIGH,
n
t
ENS
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
OE
t
DATA IN OUTPUT REGISTER
ENS
= LOW,
t
t
SKEW1
OLZ
t
ENH
t
REF
t
A
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
t
OE
(1)
EF
= HIGH
t
t
SKEW3
ENH
t
ENS
t
t
DS
A
D
(1)
1
0
NO WRITE
NO OPERATION
Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)
t
t
DHS
ENH
LAST WORD
1
2
t
WFF
t
t
DS
OHZ
t
t
DS
t
ENS
CLKH
D
D
1
X
NO OPERATION
t
WFF
t
t
ENH
DATA READ
DH
t
t
DH
CLK
2
t
CLKL
t
CLKH
t
t
REF
ENS
t
SKEW3
OLZ
t
SKEW1
t
CLK
, then
(1)
SKEW1
t
CLKL
EF
t
ENS
t
ENH
LAST WORD
FF
deassertion may be delayed one extra RCLK cycle.
t
, then the
EF
A
1
will go high (after one WCLK cycle pus t
will go HIGH (after one RCLK cycle plus t
NO WRITE
COMMERCIAL TEMPERATURE RANGE
t
FF
ENH
t
A
deassertion may be delayed one
2
NEXT DATA READ
t
t
ENS
WFF
t
DS
D
0
D
X
+1
t
REF
t
t
4674 drw 10
ENH
A
WFF
t
DH
t
WFF
4674 drw 11
17
).
REF
D
1
).