IDT72275 IDT [Integrated Device Technology], IDT72275 Datasheet - Page 9

• Manufacturer Part Number: IDT72275
• Manufacturer: IDT [Integrated Device Technology]

IDT72275/72285 SUPERSYNC FIFO™
32,768 x 18, 65,536 x 18
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
17
17
15
15
14
14
72275 (32,768 x 18–BIT)
EMPTY OFFSET REGISTER
03FFH if
FULL OFFSET REGISTER
007FH if
03FFH if
007FH if
0
0
0
X
1
1
1
DEFAULT VALUE
DEFAULT VALUE
X
0
1
1
1
0
1
is HIGH at Master Reset
is LOW at Master Reset,
is HIGH at Master Reset
is LOW at Master Reset,
X
1
0
1
1
0
1
Figure 4. Programmable Flag Offset Programming Sequence
Figure 3. Offset Register Location and Default Values
1
1
X
X
X
1
0
WCLK
X
X
X
X
0
0
RCLK
X
X
X
X
X
17
17
Parallel write to registers:
Empty Offset
Full Offset
Parallel read from registers:
Empty Offset
Full Offset
Serial shift into registers:
30 bits for the 72275
32 bits for the 72285
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
No Operation
Write Memory
Read Memory
No Operation
16
16
15
15
72285 (65,536 x 18–BIT)
03FFH if
007FH if
03FFH if
007FH if
72275
72285
EMPTY OFFSET REGISTER
FULL OFFSET REGISTER
COMMERCIAL TEMPERATURE RANGE
DEFAULT VALUE
DEFAULT VALUE
is HIGH at Master Reset
is LOW at Master Reset,
is HIGH at Master Reset
is LOW at Master Reset,
4674 drw 07
4674 drw 06
9
0
0