S29CD016G SPANSION, S29CD016G Datasheet - Page 17

• Manufacturer Part Number: S29CD016G
• Description: 16 Megabit (512 K x 32-Bit) CMOS 2.5 Volt-only Burst Mode / Dual Boot / Simultaneous Read/Write Flash Memory
• Manufacturer: SPANSION

November 5, 2004 S29CD016_00_A4
Automatic Sleep Mode (ASM)
cycle timing applies in this mode. Refer to
information.
I
fication for erase or program modes. The
contains timing specification tables and timing diagrams for erase or program
operations.
When in Synchronous read mode configuration, the device is able to perform both
asynchronous and synchronous write operations. CLK and ADV# address latch is
supported in synchronous programming mode. During a synchronous write oper-
ation, to write a command or command sequence, (which includes programming
data to the device and erasing sectors of memory), the system must drive ADV#
and CE# to VIL, and OE# to VIH when providing an address to the device, and
drive WE# and CE# to VIL, and CE# to VIH, when writing commands or data.
Accelerated Program and Erase Operations
The device offers accelerated program/erase operations through the ACC pin.
When the system asserts V
ters the Unlock Bypass mode. The system may then write the two-cycle Unlock
Bypass program command sequence to do accelerated programming. The device
uses the higher voltage on the ACC pin to accelerate the operation. A sector that
is being protected with the WP# pin is still protected during accelerated program
or Erase. Note that the ACC pin must not be at V
than accelerated programming, or device damage may result. When accelerated
program/erase is not in use, set ACC=V
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the au-
toselect mode. The system can then read autoselect codes from the internal
register (which is separate from the memory array) on DQ7–DQ0. Standard read
cycle timings apply in this mode. Refer to the
“Autoselect Command” on page 44
The automatic sleep mode minimizes Flash device energy consumption. While in
asynchronous mode, the device automatically enables this mode when addresses
remain stable for t
CE#, WE# and OE# control signals. Standard address access timings provide
new data when addresses are changed. While in sleep mode, output data is
latched and always available to the system. While in synchronous mode, the de-
vice automatically enables this mode when either the first active CLK level is
greater than t
eration is required to provide new data.
I
rent specification.
Standby Mode
When the system is not responding or writing to the device, it can place the de-
vice in the standby mode. In this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance state, independent of the OE#
input.
CC2
CC8
in the “DC Characteristics” section represents the automatic sleep mode cur-
and I
CC3
A d v a n c e
in the DC Characteristics table represents the active current speci-
ACC
or the CLK runs slower than 5 MHz. Note that a new burst op-
ACC
+ 60 ns. The automatic sleep mode is independent of the
HH
I n f o r m a t i o n
(12V) on the ACC pin, the device automatically en-
S29CD016G
sections for more information.
ss
“AC Characteristics” on page 70
“Autoselect Mode” on page 18
or ACC=V
“Autoselect Mode” on page 18
HH
cc
during any operation other
.
for more
section
and
17